Jagadeesh Mummana

This post walks through the complete optimization journey of a single-issue pipelined RV32I core, from a plain five-stage implementation all the way to a version that runs within 2.3% of a superscalar design on CoreMark. Every number here comes from actual simulation runs on my own implementation. This is not a theoretical survey – it is what happened, step by step, with real cycle counts.

Before getting into the details, a disclaimer worth repeating throughout: modern high-performance processors like those from ARM, Intel, or Apple are not just superscalar, they are wide out-of-order superscalar with speculative execution, branch prediction trained on billions of cycles of silicon, register renaming, reorder buffers, and execution units that would make what is described here look like a toy. That context matters, and so does what this comparison intentionally excludes. All CoreMark/MHz figures here are frequency-normalized because superscalar and superpipelined designs face harder timing closure, with wider forwarding muxes, more register file ports, and longer critical paths. Collapsing everything into a single clock frequency number would obscure the microarchitectural comparison. The goal here was never to match a Cortex-A or an M-series core.