Jagadeesh Mummana
Visakhapatnam, India
Electronics undergrad exploring chip design, robotics, and real-world ML systems. This is my little corner of the internet, where you’ll find my work, ideas, and experiences.
Education
National Institute of Technology Calicut (NITC)Bachelor of Technology in Electronics and Communication Engineering
2023 - 2027 | Calicut, Kerala, India
Grade: 8.51/10 (CGPA)
Lab Involvement
RIGNITC - Robotics Interest Group @ NITCTechnical Member
Nov 2024 - Present
Kerala, India
Working on several real-world interdisciplinary projects as part of robotics enthusiast teams while representing the institute on competitive platforms
School of Electrical and Computer Sciences @ IIT BBSSummer Research Intern
May 2026 - July 2026
Odisha, India
FPGA/ASIC-Optimized RTL Automation and Comparative Hardware/Statistical Evaluation of LFSR-Derived and Cellular Automaton-Based PRPG Architectures in BIST
Summer Project Member
Apr 2025 - July 2025
Kerala, India
Trained models for MRI-based Alzheimer’s & MCI classification
Featured Projects
INT8 Fixed-Point CNN Hardware Accelerator and Image-Processing Suite
Designed and implemented a quantized Res-CNN with hardware acceleration, fixed-point analysis, ROM automation, and AXI-Stream image processing blocks.
View Project
Two-Stage CMOS Op-Amp with Miller Compensation
Designed and analyzed a two-stage CMOS op-amp with Miller compensation and measured small-signal and stability metrics.
Autonomous Drone for GNSS-Denied Environments (ISRO IRoC-U 2025)
Designed and validated a quadrotor platform for GNSS-denied navigation with visual–inertial localization and simulation.
View ProjectFeatured Blogs
September 11, 2026
Intuition Behind Out-of-Order Execution and How Tomasulo Works
This post is a continuation of the RISC-V pipeline optimisation post. That post took rv32i-pipe from a CPI of 1.3158 to 1.0675 and the dual issue rv32i-superscalar to 0.7271. This post asks what comes next: what out of order execution actually is, how Tomasulo’s scheme works block by block, and what happened when it was built and measured on the same RV32IM cores with the same benchmark. Theory first, then numbers. Every number here comes from simulation runs on my own implementations, and every CoreMark figure is from Verilator.
