Jagadeesh Mummana
Visakhapatnam, India
Electronics undergrad exploring chip design, robotics, and real-world ML systems. This is my little corner of the internet, where you’ll find my work, ideas, and experiences.
GuestbookEducation
Bachelor of Technology in Electronics and Communication Engineering
2023 - 2027 | Calicut, Kerala, India
Grade: 8.66/10 (CGPA)
Lab Involvement
Technical Member
Nov 2024 - Present
Kerala, India
Working on several real-world interdisciplinary projects as part of robotics enthusiast teams while representing the institute on competitive platforms
Featured Projects
INT8 Fixed-Point CNN Hardware Accelerator and Image-Processing Suite
Designed and implemented a quantized Res-CNN with hardware acceleration, fixed-point analysis, ROM automation, and AXI-Stream image processing blocks.
View Project
Two-Stage CMOS Op-Amp with Miller Compensation
Designed and analyzed a two-stage CMOS op-amp with Miller compensation and measured small-signal and stability metrics.
Autonomous Drone for GNSS-Denied Environments (ISRO IRoC-U 2025)
Designed and validated a quadrotor platform for GNSS-denied navigation with visual–inertial localization and simulation.
View ProjectBlogs
April 20, 2026
My First Tiny Tapeout: Building a Digital PLL on Sky130
Tiny Tapeout is a shared multi-project wafer service. You submit a small digital design, it gets placed on a tile alongside hundreds of others, and the whole thing goes to a foundry on the SkyWater 130 nm open-source process. Each participant gets a rectangular slice of the die routed to a standardised interface. A 1x1 tile is roughly 160 by 100 micrometres of core area. You write RTL, push to a GitHub repository, the CI runs OpenLane against your design, and if placement and routing close within the tile boundary you get a GDS file. If the shuttle fills, that GDS goes to the fab.
