Jagadeesh Mummana
Visakhapatnam, India
Electronics undergrad exploring chip design, robotics, and real-world ML systems. This is my little corner of the internet, where you’ll find my work, ideas, and experiences.
GuestbookEducation
Bachelor of Technology in Electronics and Communication Engineering
2023 - 2027 | Calicut, Kerala, India
Grade: 8.66/10 (CGPA)
Lab Involvement
Technical Member
Nov 2024 - Present
Kerala, India
Working on several real-world interdisciplinary projects as part of robotics enthusiast teams while representing the institute on competitive platforms
Featured Projects
INT8 Fixed-Point CNN Hardware Accelerator and Image-Processing Suite
Designed and implemented a quantized Res-CNN with hardware acceleration, fixed-point analysis, ROM automation, and AXI-Stream image processing blocks.
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Two-Stage CMOS Op-Amp with Miller Compensation
Designed and analyzed a two-stage CMOS op-amp with Miller compensation and measured small-signal and stability metrics.
Autonomous Drone for GNSS-Denied Environments (ISRO IRoC-U 2025)
Designed and validated a quadrotor platform for GNSS-denied navigation with visual–inertial localization and simulation.
View ProjectBlogs
May 15, 2025
Why RISC-V Is Better for Custom Silicon
RISC-V is not automatically better than ARM or x86 for every product. It is better when you need architectural control: choose only the ISA features you need, verify a smaller design, and avoid ISA licensing constraints.
ISA first: what RISC-V actually defines
An ISA is the software-hardware contract: instructions, registers, privilege model, memory ordering, and exception behavior. Microarchitecture is separate. Pipeline depth, out-of-order logic, branch predictors, and cache policy are implementation choices.
January 17, 2025
My RosConIN'24 (+GNOME Asia Summit) Experience
January 3, 2025