About Me
I’m from Visakhapatnam, Andhra Pradesh, and currently a junior at NIT Calicut, studying Electronics and Communication Engineering.
As an electronics student, I mainly work on digital and mixed-signal hardware design, along with computer architecture and optimization. I spend most of my time building RTL blocks, writing testbenches, and using both industry and open-source EDA flows. I take designs through synthesis, timing analysis, and basic physical stages. I try to break my own designs in whatever ways possible, and most of my understanding comes from debugging and fixing them.
On the analog side, I design circuits like amplifiers, filters, and data converters, with focus on practical behavior like noise, offset, speed, and stability. I like looking at device-level physics and how it actually affects circuit behavior.
In my personal time, I contribute to and build on open-source hardware flows, and take part in competitions and design challenges where I work on smaller systems and implementations to test ideas outside structured projects. I am also involved in robotics and computer vision work through my college’s Mechatronics Lab.
I’m actively seeking internship / full-time opportunities in electronics and hardware roles. To build toward that, I am working on a few projects and learning by building and debugging them, while strengthening my fundamentals.
If you have an open role and think I might be a fit, feel free to reach out. I can share my resume and other details as needed.
My Blog
This blog is a place where I document things I learn while working on my projects. Most of what I write comes from small issues, mistakes, and debugging sessions that helped me understand something better.
I focus on parts of the process, things I explored, what I learned along the way, and how I improved them through debugging. Some posts may cover specific components or small sections of a larger project rather than the whole system.
The goal is mainly to keep a record for myself, while also sharing notes that might be useful to others working on similar problems.
Education
Bachelor of Technology in Electronics and Communication Engineering
Minor in Robotics and Automation
Intermediate (+2) - Physics, Chemistry, Mathematics
- JEE Mains 2023: 98.81 %ile | CRL 13.9K | OBC 3.2K
Matriculation (ICSE)
Lab Involvement
Technical Member
- Worked on insitute-funded interdisciplinary projects as part of robotics enthusiast teams
- Represented NITC in national and international-level competitions
- Assisted in lab visits and project exhibits; co-organised ORIGO Annual Robotics Workshops for 1st year students
- Maintainer: Website, Shared Codebase & Tech blog
- Competitions & Challenges:
- - ISRO IRoCU 2025 (Top 24 teams in India): GNSS Denied Autonomous Drone
- - IITB eYRC 2026: (AIR 13 India): FPGA Based Maze Exploration Robot
- - CDAC & RSET CarbonX 2026: (AIR 1 India): FPGA impementation of RV32I Superscalar Processor & Perf Evaluation
Summer Research Intern
- Supervisor: Dr. Ayan Palchaudhuri | Chip Design Simulation Lab, IIT Bhubaneswar
- Compared 9 PRNG architectures spanning LFSR variants and cellular automata across hardware and randomness metrics
- Proposed 2 novel intermediate architectures bridging LFSR and CA designs with tunable hardware–randomness tradeoffs
- Optimized FPGA implementations via SRL inference, LUT6_2 packing, and placement-constrained column layouts
- Investigated ASIC optimizations through XOR reduction, logic sharing, fanout management, and synthesis-driven timing
- Evaluated 81 seed–architecture combinations using NIST, correlation, entropy, and ISCAS-85 fault coverage analyses
- Automated RTL + testbench generation and cross-variant evaluation via a packaged Python CLI tool
Summer Project Member
- Supervisor: Dr. Sudhish N George
- MRI-based Alzheimer’s & MCI classification: 3D CNNs (PyTorch/MONAI, Med3DNet) with DICOM/NIfTI preprocessing
- Performance: Bayesian-tuned 3D convolutions with radiomic features achieving >93% accuracy on volumetric MRI
