Accomplishments

India Semiconductor Workforce Development Program Fellowship – Grade I Awardee

Individual Jun 2025 - Sept 2025

Selected as Grade I Fellow from 2,800+ applicants.
Completed a 3-month multi-level program covering semiconductor physics, TCAD, and fabrication processes.
Modeled semiconductor devices using Synopsys Sentaurus TCAD with geometry and doping parameterization.
Automated simulations using Sentaurus Workbench and command-based scripting.
Analyzed electrical characteristics, carrier behavior, and field profiles using Sentaurus Inspect and Visual.
Recognized among Top Performers of Cohort 5 Custom Module on Electrical Characterization of Material and Device by Tektronix.

Certified Top Performer (Analog Track) | Texas Instruments – TI BYTE Program

May 2025 - July 2025

Analog electronics fundamentals, including circuit analysis, & hands-on simulation exercises

FIR Accelerator SoC Proposal Accepted – Microwatt Momentum (OpenPOWER Hardware Design Hackathon)

Individual Proposal 2025

Proposal for a parameterizable FIR accelerator SoC accepted at the Microwatt Momentum international hardware design hackathon.
Designed a low-power DSP accelerator with configurable taps and coefficients using a Wishbone-Lite interface.
Shortlisted for potential fabrication consideration via ChipFoundry and Efabless OpenMPW Shuttle.

ISRO IROC-U Robotics Challenge – Elimination Round Qualifier

Team Dec 2024 Top 24 Nationally

Ranked Top 24 nationally in IRoC-U 2025.
Built an autonomous drone system for GNSS-denied navigation and surface mapping.
Participated in national-level elimination rounds.

FPGA-Based Maze Solver, e-Yantra Robotics Competition (IITB eYRC'26)

Team Oct 2025 - Feb 2026 All India Rank 13

Built and verified a 32-bit RISC-V single-cycle core (32x32 regfile, full load/store ISA) in Verilog on Cyclone-IV FPGA (DE0 Nano); Fmax 112 MHz.
Integrated ultrasonic and IR sensors for wall detection and obstacle avoidance, with temperature, humidity, and soil moisture sensing for warehouse microclimate data acquisition.
Implemented motor control, UART telemetry, and wireless communication to Central Control Unit running in parallel on the custom CPU.
Validated full system through sensor calibration routines and live maze runs.

RV32I CPU Design, HackS'US-V Vegathon (RSET IEDC & C-DAC Thiruvananthapuram)

Team Mar 2026 1st Place, National | 42hr Hackathon

Designed and compared four RV32I core variants: single-cycle, multi-cycle, 5-stage pipeline (IF-ID-EX-MEM-WB), and dual-issue in-order superscalar.
Superscalar core: two-wide fetch, parallel pipelines, inter-lane RAW/WAW hazard detection, load-use stalls, branch squash, 4R2W regfile, and multi-port memory.
Evaluated CPI, IPC, and latency across variants using performance counters.
Synthesized and demonstrated on Spartan-7 FPGA with LUT utilization comparison across microarchitectures.

Global Placement Optimization, Macro Placement Challenge '26 (Partcl and HRT, IBM Benchmark Suite ICCAD04)

Team 2026 WR Rank 50 | Proxy: 1.3241 | Overlaps: 0

Benchmarked on the IBM Benchmark Suite (ICCAD04), where each case includes hard macros to be placed, soft macros that can also be placed, nets connecting all components, and a hand-crafted initial placement used as reference.
Achieved a proxy score of 1.3241 with zero macro overlaps, ranked 50 on the world ranking leaderboard.
Outperformed RePlAce (proxy 1.4578) and simulated annealing baseline (proxy 2.1251).
Built a multi-phase placement pipeline: legalization from initial placement, followed by a WL thermostat using simulated annealing on a sparse pair graph with overlap-safe moves.
Applied coarse-to-fine coordinate descent with exact proxy evaluation for refinement.
Implemented Large Neighborhood Search (LNS): destroy and repair of connected-macro patches, accepting moves only on proxy improvement.
Ran a final soft-macro force-directed pass on the best hard placement found.
Used multi-start optimization (3 restarts) with Gaussian perturbation, keeping the global best result across runs.

Design Events

Electronics Design Events — Tathva Annual Tech Fest, NIT Calicut

Team

Circuit Conclave (Analog Circuit Design & Debugging): 1st Place (Tathva ’24), 3rd Place (Tathva ’25).
Disarmamine (Digital Circuit Design & Debugging): 3rd Place (Tathva ’24).

Digital Circuit Design Challenge (DCDC) — NIT Trichy, Probe ’25

Team Qualified for Round 2 (Digital logic design, Verilog, Xilinx Vivado testbench debugging).

Analog Circuit Design Challenge (ACDC) — IIT Madras, Shastra ’26

Team Qualified for Round 2 (Op-amps, amplifiers, CMOS circuit analysis).

Robotics and ML Challenges

Robotrix ’24 — NIT Surathkal

Individual Dec 2024 Round 1 Qualified

Developed stereo vision-based 3D control pipeline for dynamic object interception.
Implemented disparity-based 3D reconstruction and projectile motion prediction.
Controlled 3-axis actuated system using independent PID loops in CoppeliaSim (24-hour simulation round).

Flipkart GRiD 6.0 Robotics Challenge — Smart Vision Quality Analysis

Individual Aug 2024 Round 1 Qualified

Built vision-based grocery quality and quantity analysis system.
Constructed multi-domain dataset using Roboflow pipelines.
Trained YOLOv7-based detection model for classification and counting.
Implemented OCR-driven validation and freshness assessment logic.

AWS Student DeepRacer Program — Reinforcement Learning & Autonomous Driving

Individual Mar 2024

Completed AI/ML coursework under AWS AI/ML Scholarship (Udacity & Amazon).
Trained PPO-based reinforcement learning models using AWS DeepRacer and Amazon SageMaker.
Placed on the global leaderboard in AWS AI/ML Global Student League.

Other Hackathons and Challenges

Hardware-Accelerated CNN on FPGA, Bharat AI-SoC Challenge (ARM & C2S India)

Team Jan 2026 Ongoing

Explored 8 CNN architectures on CIFAR-10; selected Pareto-optimal ResNet-style model (52k params, 12.6M FLOPs, 80-84% accuracy) for hardware deployment.
Applied PTQ and QAT quantization (Q1.7 fixed-point); 4x memory reduction with <1% accuracy loss across MODEL ARCH 4 (72k params) and MODEL ARCH 8 (52k params).
Full Verilog RTL CNN: parametric conv2d, max-pool, residual/shortcut add (1x1 conv), GAP, dense, softmax in Q7 fixed-point; FSM-controlled with two-cycle ready/valid handshake; validated end-to-end at 84% accuracy (100 CIFAR-10 images, FP32 and Q1.7).
Systolic array GEMM and Conv2D: 9-PE CSA-MBE MAC array with Booth multiplier and CSA tree reduction, 3-stage pipeline; benchmarked CSA/Kogge-Stone/RCA adders and MBE/Booth/Baugh-Wooley multipliers on Sky130 RTL2GDS (Yosys/OpenSTA) based on fmax, power and area; GDS and layouts generated.
Streaming Zynq-7000 architecture with AMBA AXI: AXI4-Lite for runtime weight/bias loading from DDR, AXI-Stream for pixel ingestion with FIFO decoupling, AXI-Lite for control; first convolution layer validated against Python golden model (+-1 LSB rounding deviation).
SW baselines on PYNQ ARM Cortex-A9: NumPy inference (~21s/image FP32, ~30s/image Q1.7); keras2c evaluated across baseline, loop-pragma, and graph-fused variants (residual fusion, tensor materialization reduction) at O0-Ofast; best ~361ms/image.
hls4ml (Vivado HLS, ap_fixed<16,6>, ReuseFactor=32, Resource strategy) and Vitis HLS (ap_fixed<16,8>, AXI-MM + AXI-Lite) explored for HLS-based acceleration.
Brevitas QAT (4-bit weights/activations, 8-bit input) + FINN 17-stage dataflow compilation targeting Zybo Z7-10 (xc7z010clg400-1); custom board integration, AXI-Stream + AXI-Lite PS-PL; post-synthesis: 11,581 LUT, 14,557 FF, 17 BRAM36K, 3 DSP; bitstream generated.
Vitis HLS kernel on xc7z020: 18,379 LUT (34%), 243 BRAM_18K (86%), 22 DSP (10%), Fmax 136.99 MHz.

C2S Chip to Startup Digital Hackathon

Team Feb 2025

Participated in digital electronics-focused hackathon under MeitY initiative.

Nokia FPGA Hackathon

Team Mar 2025

Participated in FPGA-based quiz (Round 1).

Bajaj Auto Ohm Challenge

Team Feb 2025

Engineering competition emphasizing electrical and electronic innovation.

Bharatiya Antariksh Hackathon (BAH ’24)

Team July 2024

Developed AI/ML-based crater and boulder detection system using OHRC imagery.

Bit N Build Around The World 2024

Individual Oct 2024

24-hour hackathon; developed city traffic prediction system using computer vision.