Blogs

October 15, 2026

An Intuitive Look at Tomasulo, RV32IM Out-of-Order Implementation and Optimisation hardware riscv computer-architecture rtl

This post is a continuation of the RISC-V pipeline optimisation post. That post took rv32i-pipe from a CPI of 1.3158 to 1.0675 and the dual issue …

Superscalar OoO Tomasulo

September 30, 2026

Running FreeRTOS on a RISC-V Core hardware riscv computer-architecture rtl

This post documents the implementation, debugging, and verification required to run FreeRTOS and an interactive command-line interface on the dual-issue RV32IM …

Superscalar FreeRTOS RTOS

September 20, 2026

DOOM on Bare-Metal FPGA hardware riscv computer-architecture fpga

The core was validated in Verilator with a dual issue in order RV32IM pipeline, a hybrid predictor, a BTB, and a return address stack. A DOOM gameplay workload …

FPGA DE0-Nano Cyclone IV

September 12, 2026

Xilinx vs Altera FPGAs hardware FPGA

An FPGA is a grid of logic and programmable wires. You load a bitstream and the chip becomes whatever circuit you described. Basic elements Every FPGA, Xilinx …

FPGA Xilinx Altera

September 7, 2026

Reverse Engineering the Jane Street ASIC Puzzle hardware asic reverse-engineering verilog

Jane Street released an ASIC reverse engineering puzzle in August 2026. They taped out a chip on the SkyWater 130 nm open PDK and published the final GDS, plus …

GDS SKY130 SkyWater

July 5, 2026

Can It Run DOOM? YES!! hardware riscv computer-architecture rtl

This blog is the complete record of a project that runs DOOM on a superscalar RISC-V core. The core and its peripheral bridge are plain synthesizable Verilog …

Superscalar DOOM Can It Run DOOM

June 20, 2026

Building a Macro Placer for the HRT Global Placement Challenge hardware global placement asic openroad

The HRT global placement challenge (partcleda/macro-place-challenge-2026) scores submissions on a proxy cost of WL + 0.5*Density + 0.5*Congestion across the 17 …

placement algo algorithms machine learning

June 6, 2026

DFT Scan Insertion on a NoC Router: Working Around OpenLane 2's Missing DFT Support rtl-design physical-design asic

OpenLane 2’s Classic flow has no DFT steps. Not reduced DFT support, not a partially working implementation: none. Running Step.factory.list() against the …

DFT scan insertion OpenLane 2

May 10, 2026

Building a Hardware Scan-Line Triangle Rasterizer: From Single-Pixel Core to SIMD Warp Architecture rtl-design graphics fpga

Pre-shader fixed-function rasterization architectures are well-documented at the block-diagram level but seldom implemented from scratch outside of academic or …

SystemVerilog rasterization fixed-point arithmetic

April 20, 2026

My First Tiny Tapeout: Building a Digital PLL on Sky130 hardware computer-architecture rtl

Tiny Tapeout is a shared multi-project wafer service. You submit a small digital design, it gets placed on a tile alongside hundreds of others, and the whole …

CORDIC DPLL FFT

April 5, 2026

Optimising a Pipelined RISC-V Core: From Naive Pipeline to Near-Superscalar Performance hardware riscv computer-architecture rtl

This post walks through the complete optimization journey of a single-issue pipelined RV32I core, from a plain five-stage implementation all the way to a …

Superscalar OoO CoreMark

March 28, 2026

Hardware Approaches to Floating-Point Transcendental Function Computation: CORDIC, PR-CORDIC, and LUT+Polynomial hardware computer-architecture rtl fpga

Computing sin(x), cos(x), arctan(x), e^x, and ln(x) in hardware is not as obvious as it sounds. Software on a general-purpose CPU offloads these to a …

CORDIC transcendental IEEE-754

March 15, 2026

Formal Verification with SymbiYosys and Yices2: Proving Your RTL Correct hardware rtl computer-architecture verification

Simulation tells you what happened in the cases you thought of. Formal verification tells you what happens in every case that can ever occur. That difference …

formal verification SymbiYosys yices2

March 15, 2026

The RISC-V Ecosystem: Toolchains, Open-Source Cores, and Production Silicon hardware riscv computer-architecture open-source

The architectural case for RISC-V rests on modularity: a clean base integer instruction set surrounded by optional standard extensions. However, an ISA is only …

RISC-V Ecosystem Compilers

March 5, 2026

Packaging RTL IP with FuseSoC: From ALU to Published Core hardware rtl tools

If you have spent any time doing RTL development, you have probably dealt with the nightmare of managing HDL source lists manually. passing filelist arguments …

fusesoc ip packaging verilog

February 27, 2026

Setting Up PYNQ on Legacy Zybo (xc7z010clg400-1): Complete Boot and WiFi Guide hardware zynq embedded-linux

Getting PYNQ running on the original Zybo takes more work than the official documentation suggests, because the official documentation does not target this …

PYNQ Zynq-7000 Zybo

January 25, 2026

High-Level Synthesis with C: A Practical Guide from Code to RTL hardware fpga hls

High-level synthesis takes a C or C++ function and produces synthesizable RTL from it. Vitis HLS and the older Vivado HLS are the dominant tools in the Xilinx …

HLS Vitis HLS Vivado HLS

January 4, 2026

PD-aware Machine Learning: Congestion, DRC, IR-Drop and Net Delay Prediction physical-design eda machine-learning

Machine learning in physical design (PD) is not about replacing routing or timing engines. It is about predicting expensive post-route outcomes earlier in the …

physical design EDA ML congestion prediction