Xilinx vs Altera FPGAs

An FPGA is a grid of logic and programmable wires. You load a bitstream and the chip becomes whatever circuit you described.

Basic elements

Every FPGA, Xilinx or Altera, is built from five pieces.

LUT - Look-Up Table. A tiny SRAM that stores a truth table. Inputs are the address, stored bit is the output. Change the stored bits, same hardware becomes a different gate.

A 2-input LUT is 4 bits of SRAM:

a b | stored bit | address
0 0 |  0         | 00
0 1 |  0         | 01
1 0 |  0         | 10
1 1 |  1         | 11

bits = 0001 -> AND
bits = 0111 -> OR
same 4 SRAM cells, different function

A LUT4 stores 16 bits, a LUT6 stores 64 bits. A 6-input LUT can implement any function of 6 inputs in one level and one LUT delay. The bitstream is mostly filling these tables and setting routing switches.

LUT6
  inputs: I0-I5
  +--------------+
  | 64x1 SRAM    |  truth table
  | mux tree     |
  +--------------+
  outputs: O6 (6-input), O5 (5-input)
  one LUT6 can be two LUT5 sharing I0-I4

Flip-flop. A 1-bit register that captures D on a clock edge and holds Q. In an FPGA the flip-flop is separate silicon next to the LUT and can be used or bypassed independently. LUT computes, flip-flop stores.

FF
  inputs: D, CLK, CE, SR
  output: Q

Carry chain. Addition needs carry from bit 0 to 1 to 2. Through general routing this would be slow. FPGAs add a private vertical wire between stacked slices or ALMs with dedicated muxes and XORs. Carry skips general routing entirely. One bit costs about 10-30 picoseconds.

Writing it the wrong way leaves it unused:

// hand-built lookahead - correct logic, wrong for FPGA
// built from LUTs + general routing, ~96 LUTs for 32-bit
logic [31:0] g = a & b;
logic [31:0] p = a ^ b;
logic [32:0] c;
always_comb begin
  c[0] = cin;
  for (int i=0;i<32;i++) c[i+1] = g[i] | (p[i] & c[i]);
end
assign sum = p ^ c;

// what you should write
assign {cout, sum} = a + b + cin;
// tool maps to CARRY4/CARRY8 + LUTs, ~32 LUTs + 8 CARRY4, ~1.2 ns for 32-bit

Same rule for subtract, compare, and increment. Write the operator.

Memory. Two kinds.

Distributed RAM uses LUT SRAM as tiny memory. In Xilinx, a SLICEM LUT6 is 64x1 RAM. In Altera, 10 ALMs become 640-bit MLAB.

Block RAM is a hardened SRAM tile. More efficient for larger buffers.

A common misconception is Altera has no true dual-port. Cyclone V and newer M10K/M20K are true dual-port.

DSP block. Hardened multiply-accumulate. P = A*B + C with pre-adder and accumulator. A variable multiply would take hundreds of LUTs. DSP does it in one block.

DSP48 (Xilinx) / Variable Precision (Altera)
  inputs: A (18-27b), B (18b), C (48b), D for pre-add
  output: P = (A +/- D) * B + C

Constant multiply like a * 5 often becomes shift-add in LUTs and is cheaper than DSP.

Xilinx: CLB and Slice

Xilinx groups into Slice, then CLB. A CLB is the tile the placer moves. The idea exists because a single slice is not associated with a routing switchbox, two slices share one. From UltraScale onward, 1 CLB = 1 slice but the slice is twice as large.

7-Series Slice (4 LUT6 + 8 FF)
  inputs : 4x I0-I5 (24), CLK, CE, SR, CIN
  +---------------------------------+
  | 4x LUT6 -> O5/O6                |
  | F7MUX combines 2 LUT6 -> 7-in   |
  | F8MUX combines 2 F7 -> 8-in     |
  | CARRY4: 4-bit fast carry        |
  | 8x FF: D -> Q                   |
  +---------------------------------+
  outputs: 4x O6, 4x O5, 8x Q, COUT

CLB (7-Series) = 2x Slice above
  inputs : ~56 from routing
  outputs: ~24 to routing + carry

SLICEL is logic only. SLICEM can have its LUTs as 64x1 RAM or 32-bit shift register SRL32. About a third of slices are SLICEM. Using many distributed RAMs can fill SLICEMs locally even at low global utilization.

UltraScale:

UltraScale Slice
  inputs : 8x I0-I5 (48), 4x CLK/CE/SR, CIN
  8x LUT6 + 16x FF + CARRY8
  bypass for all 16 FFs -> FF without LUT costs 0 LUTs
  CLB = 1 Slice, 64 inputs / 32 outputs

Versal: CLB = 4 Slices (2 SLICEL + 2 SLICEM), each 8 LUT6 + 16 FF, no wide F7/F8. Fabric now sits around hard Network-on-Chip, AI Engines, and DSP58.

Altera: LAB, LE, and ALM

Old block is LE, used in Cyclone III/IV and MAX:

LE
  inputs : 4 from LAB, carry-in, CLK, ENA, CLR
  1x LUT4 -> comb
  1x FF
  outputs: comb + Q + carry-out

LAB (LE-based, Cyclone IV)
  16x LE
  inputs: ~48 from routing

New block is ALM since Stratix II in 2004, used in Cyclone V, Arria 10, Stratix 10, Agilex:

ALM
  inputs : 8 shared a-h
  2x ALUT (fracturable)
    modes: 2x LUT4, or 5+3, or 6 with 2 outs, or 7-input
  2x full adder
  2x FF (4x FF from Stratix V)
  outputs: 2 comb + 2-4 Q + carry

LAB (ALM-based)
  10x ALM
  inputs: ~60 from routing
  50% of LABs can be MLAB: 640-bit RAM

One ALM is about 2.5 LEs. Two 4-input functions can fit in one ALM by using both ALUTs. That is the area efficiency Altera targets for control logic.

Same idea, different names

Xilinx slices have higher register-to-LUT ratio, 2:1, better for pipelined datapaths. Altera ALMs have flexible fracturing, better for narrow control logic. Below ~70% utilization both close timing easily. At high utilization Xilinx denser short routing helps, Altera HyperFlex helps.

Xilinx families

Spartan was cost version of older Virtex. Spartan-3 (90nm, 4-LUT) and Spartan-6 (45nm, 6-LUT) were ISE parts. Spartan-7 is 7-Series fabric, same 6-LUT slice as Artix-7, but no transceivers.

Artix is low-cost with transceivers. Artix-7 is 28nm with GTP up to 6.6 Gbps. Artix UltraScale+ moves to 16nm with GTH/GTY up to 32 Gbps.

Kintex is mid-range for price/performance. Kintex-7, Kintex UltraScale (20nm), Kintex UltraScale+ (16nm) have more DSP48 and BRAM than Artix, plus UltraRAM. Used for video and packet processing.

Virtex is high-end. Virtex-7, Virtex UltraScale, Virtex UltraScale+ are largest parts, using stacked silicon interposer to combine multiple dies with 10k+ wires between them. UltraScale+ has HBM2 variants with in-package DRAM up to 460 GB/s.

Zynq adds hard ARM. Zynq-7000 pairs 7-Series with dual Cortex-A9. Zynq UltraScale+ MPSoC pairs UltraScale+ with quad A53 and dual R5. RFSoC adds multi-GSPS ADCs and DACs.

Versal is ACAP: scalar ARM A72/R5F, adaptable fabric, AI Engine vector, DSP58, and hard NoC. CLB is 4 slices.

Altera families

MAX is CPLD and small flash FPGA. MAX 7000, MAX II, MAX V are CPLDs. MAX 10 is 55nm flash with instant-on and ADC.

Cyclone is low-cost. Cyclone III/IV are LE-based with M9K RAM. Cyclone V shifts to ALM with M10K and dual A9 SoC. Cyclone 10 LP is 60nm low-power refresh, Cyclone 10 GX is 20nm with transceivers.

Arria is mid-range with transceivers. Arria II, Arria V, Arria 10 with hard FP32 and 17 Gbps transceivers.

Stratix is high-end. Stratix II introduced ALM in 2004. Stratix III/IV/V grew to 10 ALMs per LAB with 4 FFs per ALM. Stratix 10 introduced HyperFlex, which puts bypassable registers on every routing segment and block input for automatic retiming.

Agilex is current 10nm. Agilex 3 low-end replacing Cyclone V with dual A55, Agilex 5 mid-range with AI Tensor Blocks for INT8, Agilex 7 high-end F/I/M with 116G PAM4 and PCIe Gen5, Agilex 9 direct RF with 64 GSPS converters.

How to read the part number

Xilinx XC7A100T-2FGG484C:

• XC = Xilinx Commercial
• 7 = 7-Series
• A = Artix, K = Kintex, V = Virtex, S = Spartan, Z = Zynq
• 100T = density, T = transceivers
• -2 = speed grade
• FGG484 = package and pins
• C = commercial, I = industrial

Altera 10AX115N3F45E2SG:

• 10 = 10th generation
• AX = Arria 10 GX, CE = Cyclone V E, e.g. 5CEFA7 is Cyclone V E ~56K LE
• 115 = density
• N3 = speed grade
• F45 = 1152-ball FBGA

Agilex AGF027H4F40I3E = Agilex 7 F-series 270K LE, H4 package, I3 speed.

Where Xilinx and Altera sit

Xilinx and Altera together are most of FPGA revenue, roughly half for Xilinx and about a third for Altera. That is why most comparison is between these two.

A note on others: Lattice is third largest and usual pick for low-power small packages with iCE40, ECP5, MachXO. Microchip with PolarFire and IGLOO is common in aerospace and defense for flash and long lifecycle. Efinix with Trion and Titanium and Gowin with GW1N and Arora are lower-cost options on hobby boards.

References

• fpgakey.com - Briefly on difference between Altera and Xilinx FPGA - CLB with 2 Slices, LAB with 8 ALM, TriMatrix M512/M4K/M-RAM
• limchip.com - Altera vs Xilinx Architecture Comparison - ALM vs Slice register ratio 2:1 vs fracturing, routing and true dual-port note
• blinknbuild.in - FPGA Architecture: LUTs, Slices, Block RAM & DSP - LUT6 as 64 bits and mux tree, carry chain 10-30 ps, distributed vs BRAM vs UltraRAM table, DSP pitfalls
• ecrionix.org - Day 2: Inside an FPGA - LUT as truth table memory, 2-input LUT as 4-entry, bitstream fills tables
• University of Belgrade ETF - Altera vs Xilinx comparative analysis - LC vs LE naming, ALM = 2.5 LE, Spartan-3 CLB with 4 slices
• reddit r/FPGA - FPGA terminology clarification - CLB exists because slice has no switchbox, 2 slices per CLB, UltraScale 1 CLB = 1 slice twice as large, LAB = 10 ALM
• Xilinx UG474 7 Series CLB and UG574 UltraScale CLB
• Altera Stratix II Logic and Routing Architecture paper