Computer-Architecture

My First Tiny Tapeout: Building a Digital PLL on Sky130

Optimising a Pipelined RISC-V Core: From Naive Pipeline to Near-Superscalar Performance

Hardware Approaches to Floating-Point Transcendental Function Computation: CORDIC, PR-CORDIC, and LUT+Polynomial

Formal Verification with SymbiYosys and Yices2: Proving Your RTL Correct

A practical walkthrough of setting up SymbiYosys and Yices2, writing SystemVerilog Assertions, and formally verifying a handshake module for deadlock, reset correctness, and protocol safety.

Designing a 4R2W Register File: Why It's Harder Than It Looks

A hands-on deep dive into building a 4-read, 2-write register file in Verilog — architectural tradeoffs, structural hazards, and practical RTL fixes.