High-Level Synthesis (HLS) with C: A Deep Practical Guide from Code to RTL
A detailed, hands-on introduction to HLS using C — understanding scheduling, pipelining, memory mapping, interfaces, and performance tradeoffs.
Fpga
Designing a Simple RTL Block for ASIC vs FPGA: A Pipelined 8-bit MAC
A practical comparison of designing the same hardware block for ASIC and FPGA — architecture, RTL style, constraints, and physical implications.