The core was validated in Verilator with a dual issue in order RV32IM pipeline, a hybrid predictor, a BTB, and a return address stack. A DOOM gameplay workload …
FPGA
DE0-Nano
Cyclone IV
category · 6 posts
FPGA
HARDWARE (22)
COMPUTER-ARCHITECTURE (10)
RTL (10)
RISCV (7)
FPGA (6)
PID (6)
PID1 (6)
RUBIKSCUBESOLVER (6)
ROBOTICS (5)
VLSI (5)
ASIC (4)
PHYSICAL-DESIGN (2)
RTL-DESIGN (2)
ALGORITHMS (1)
ANALOG (1)
BLOGGING (1)
DIGITAL-DESIGN (1)
EDA (1)
EMBEDDED-LINUX (1)
EVENTS (1)
GLOBAL PLACEMENT (1)
GRAPHICS (1)
HLS (1)
LOCALIZATION (1)
MACHINE-LEARNING (1)
MIXED-SIGNAL (1)
OPEN-SOURCE (1)
OPENROAD (1)
PERSONAL (1)
REVERSE-ENGINEERING (1)
ROS (1)
TOOLS (1)
VERIFICATION (1)
VERILOG (1)
VLA (1)
ZYNQ (1)
An FPGA is a grid of logic and programmable wires. You load a bitstream and the chip becomes whatever circuit you described. Basic elements Every FPGA, Xilinx …
FPGA
Xilinx
Altera
Building a Hardware Scan-Line Triangle Rasterizer: From Single-Pixel Core to SIMD Warp Architecture
rtl-design
graphics
fpga
Pre-shader fixed-function rasterization architectures are well-documented at the block-diagram level but seldom implemented from scratch outside of academic or …
SystemVerilog
rasterization
fixed-point arithmetic
Hardware Approaches to Floating-Point Transcendental Function Computation: CORDIC, PR-CORDIC, and LUT+Polynomial
hardware
computer-architecture
rtl
fpga
Computing sin(x), cos(x), arctan(x), e^x, and ln(x) in hardware is not as obvious as it sounds. Software on a general-purpose CPU offloads these to a …
CORDIC
transcendental
IEEE-754
High-level synthesis takes a C or C++ function and produces synthesizable RTL from it. Vitis HLS and the older Vivado HLS are the dominant tools in the Xilinx …
HLS
Vitis HLS
Vivado HLS
The multiply-accumulate operation $$ Y \leftarrow Y + (A \times B) $$is the computational primitive at the center of digital filters, CNN inference, matrix …
ASIC design
FPGA design
MAC unit