category · 22 posts
This post is a continuation of the RISC-V pipeline optimisation post. That post took rv32i-pipe from a CPI of 1.3158 to 1.0675 and the dual issue …
This post documents the implementation, debugging, and verification required to run FreeRTOS and an interactive command-line interface on the dual-issue RV32IM …
The core was validated in Verilator with a dual issue in order RV32IM pipeline, a hybrid predictor, a BTB, and a return address stack. A DOOM gameplay workload …
An FPGA is a grid of logic and programmable wires. You load a bitstream and the chip becomes whatever circuit you described. Basic elements Every FPGA, Xilinx …
Jane Street released an ASIC reverse engineering puzzle in August 2026. They taped out a chip on the SkyWater 130 nm open PDK and published the final GDS, plus …
This blog is the complete record of a project that runs DOOM on a superscalar RISC-V core. The core and its peripheral bridge are plain synthesizable Verilog …
The HRT global placement challenge (partcleda/macro-place-challenge-2026) scores submissions on a proxy cost of WL + 0.5*Density + 0.5*Congestion across the 17 …
Tiny Tapeout is a shared multi-project wafer service. You submit a small digital design, it gets placed on a tile alongside hundreds of others, and the whole …
This post walks through the complete optimization journey of a single-issue pipelined RV32I core, from a plain five-stage implementation all the way to a …
Computing sin(x), cos(x), arctan(x), e^x, and ln(x) in hardware is not as obvious as it sounds. Software on a general-purpose CPU offloads these to a …
Simulation tells you what happened in the cases you thought of. Formal verification tells you what happens in every case that can ever occur. That difference …
The architectural case for RISC-V rests on modularity: a clean base integer instruction set surrounded by optional standard extensions. However, an ISA is only …
If you have spent any time doing RTL development, you have probably dealt with the nightmare of managing HDL source lists manually. passing filelist arguments …
Getting PYNQ running on the original Zybo takes more work than the official documentation suggests, because the official documentation does not target this …
High-level synthesis takes a C or C++ function and produces synthesizable RTL from it. Vitis HLS and the older Vivado HLS are the dominant tools in the Xilinx …
An ADC is the interface between the physical world and computation. The choice of architecture determines not just the achievable resolution and speed, but the …
A register file is one of those structures that looks trivial until you actually build one. The concept is simple: a small block of fast storage inside a …
A CMOS operational amplifier is a multi-stage analog circuit that achieves high voltage gain, high input impedance, and controlled frequency response through a …
In software, numeric representation is an abstraction you rarely have to think about. The compiler handles it, the hardware handles it, and the behavior is …
RISC-V is not automatically better than ARM or x86 for every product. It is better when you need architectural control: choose only the ISA features you need, …
Turning RTL into a working chip is not a single transformation. It is a sequence of steps, each of which narrows the design from an abstract description of …
The central question in autonomous vehicle perception is how much of the sensing work to assign to cameras and learned models, and how much to delegate to …