Rtl

Packaging RTL IP with FuseSoC: From ALU to Published Core

A practical walkthrough of what an IP core actually is, how to write one in Verilog, and how to package, simulate, and publish it using FuseSoC. the build system that should have existed ten years ago.

Designing a 4R2W Register File: Why It’s Harder Than It Looks

A hands-on deep dive into building a 4-read, 2-write register file in Verilog — architectural tradeoffs, structural hazards, and practical RTL fixes.

Designing a Simple RTL Block for ASIC vs FPGA: A Pipelined 8-bit MAC

A practical comparison of designing the same hardware block for ASIC and FPGA — architecture, RTL style, constraints, and physical implications.