category · 2 posts

RTL-DESIGN

June 6, 2026

DFT Scan Insertion on a NoC Router: Working Around OpenLane 2's Missing DFT Support rtl-design physical-design asic

OpenLane 2’s Classic flow has no DFT steps. Not reduced DFT support, not a partially working implementation: none. Running Step.factory.list() against the …

DFT scan insertion OpenLane 2

May 10, 2026

Building a Hardware Scan-Line Triangle Rasterizer: From Single-Pixel Core to SIMD Warp Architecture rtl-design graphics fpga

Pre-shader fixed-function rasterization architectures are well-documented at the block-diagram level but seldom implemented from scratch outside of academic or …

SystemVerilog rasterization fixed-point arithmetic