category · 10 posts

RTL

October 15, 2026

An Intuitive Look at Tomasulo, RV32IM Out-of-Order Implementation and Optimisation hardware riscv computer-architecture rtl

This post is a continuation of the RISC-V pipeline optimisation post. That post took rv32i-pipe from a CPI of 1.3158 to 1.0675 and the dual issue …

Superscalar OoO Tomasulo

September 30, 2026

Running FreeRTOS on a RISC-V Core hardware riscv computer-architecture rtl

This post documents the implementation, debugging, and verification required to run FreeRTOS and an interactive command-line interface on the dual-issue RV32IM …

Superscalar FreeRTOS RTOS

July 5, 2026

Can It Run DOOM? YES!! hardware riscv computer-architecture rtl

This blog is the complete record of a project that runs DOOM on a superscalar RISC-V core. The core and its peripheral bridge are plain synthesizable Verilog …

Superscalar DOOM Can It Run DOOM

April 20, 2026

My First Tiny Tapeout: Building a Digital PLL on Sky130 hardware computer-architecture rtl

Tiny Tapeout is a shared multi-project wafer service. You submit a small digital design, it gets placed on a tile alongside hundreds of others, and the whole …

CORDIC DPLL FFT

April 5, 2026

Optimising a Pipelined RISC-V Core: From Naive Pipeline to Near-Superscalar Performance hardware riscv computer-architecture rtl

This post walks through the complete optimization journey of a single-issue pipelined RV32I core, from a plain five-stage implementation all the way to a …

Superscalar OoO CoreMark

March 28, 2026

Hardware Approaches to Floating-Point Transcendental Function Computation: CORDIC, PR-CORDIC, and LUT+Polynomial hardware computer-architecture rtl fpga

Computing sin(x), cos(x), arctan(x), e^x, and ln(x) in hardware is not as obvious as it sounds. Software on a general-purpose CPU offloads these to a …

CORDIC transcendental IEEE-754

March 15, 2026

Formal Verification with SymbiYosys and Yices2: Proving Your RTL Correct hardware rtl computer-architecture verification

Simulation tells you what happened in the cases you thought of. Formal verification tells you what happens in every case that can ever occur. That difference …

formal verification SymbiYosys yices2

March 5, 2026

Packaging RTL IP with FuseSoC: From ALU to Published Core hardware rtl tools

If you have spent any time doing RTL development, you have probably dealt with the nightmare of managing HDL source lists manually. passing filelist arguments …

fusesoc ip packaging verilog

October 3, 2025

Designing a 4R2W Register File: Why It's Harder Than It Looks hardware rtl computer-architecture

A register file is one of those structures that looks trivial until you actually build one. The concept is simple: a small block of fast storage inside a …

September 14, 2025

Designing a Simple RTL Block for ASIC vs FPGA: A Pipelined 8-bit MAC rtl asic fpga

The multiply-accumulate operation $$ Y \leftarrow Y + (A \times B) $$is the computational primitive at the center of digital filters, CNN inference, matrix …

ASIC design FPGA design MAC unit