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mj97@root:~$ 
mj97@root:~$ tree ./
./
├── about/
│ ├── Accomplishments
│ ├── Achievements
│ ├── Positions
│ └── Scholarships
├── projects/
│ ├── INT8 Fixed-Point CNN Hardware Accelerator and Image-Processing Suite/
│ │ ├── INT8 Hardware Accelerated CNN
│ │ ├── Bharat AI Soc Student Challenge by ARM & C2S India
│ │ ├── ImProVe: IMage PROcessing using VErilog
│ │ ├── ImProVeR: IMage PROcessing using VErilog - Revised
│ │ ├── NeVer: NEural NEtwork in VERilog
│ │ ├── Wavefront Systolic Array - GEMM, Conv2d, and MAC Physical Design Study
│ │ └── Design and Formal Verification of Fixed-Point CORDIC core
│ ├── Design & Formal Verification of Parameterizable Fixed-Point CORDIC IP/
│ │ ├── Full reports and documentation can be found here
│ │ ├── QAM16 Demodulator
│ │ ├── DPLL
│ │ ├── FFT/IFFT
│ │ ├── Sigma-Delta ADC - Bandpass IF Sampling with Downconversion
│ │ └── My First Tiny Tapeout: Designing and Hardening a CORDIC based DPLL
│ ├── Pipelined Systolic Array for GEMM/Conv2D with MAC PPA Study (Sky130 OpenLane)
│ ├── Dual-Issue Superscalar RV32I CPU: Design, Verification, and Performance Evaluation/
│ │ ├── RV32I(M) CPU Core Variants: SC / MC / Pipelined / Superscalar / Out-of-Order
│ │ ├── Dual-Issue 16-bit Superscalar RISC Processor
│ │ ├── RV32I RISC-V Core (TL-Verilog, Single-Cycle)
│ │ └── MIPS & RISC Microarchitectures (SC / MC / Pipeline)
│ ├── Low-Power 5-Port Wormhole NoC Router/
│ │ ├── Building a Hardware Scan-Line Triangle Rasterizer: From Single-Pixel Core to SIMD Warp Architecture
│ │ ├── Low-power physical design
│ │ ├── Pipelining the router datapath
│ │ ├── DFT scan chain insertion
│ │ └── ATPG on gate-level netlists
│ ├── Pipelined Low Power ALU with Scan Chain Integration
│ ├── AHB–APB Bridge with Self-Checking Verification
│ ├── Functional & UVM Verification of SHA-256 Core (secworks)
│ ├── CMOS Bandgap Reference Simulation
│ ├── Two-Stage CMOS Op-Amp with Miller Compensation
│ ├── CMOS Inverter Layout & Post-Layout Simulation
│ ├── Analog Function Generator with Adjustable Amplitude, Offset, Phase, Modulation & VCO
│ ├── Semiconductor Device Modeling using Sentaurus TCAD
│ ├── FIR DSP Accelerator SoC (Sky130, Caravel)
│ ├── Fixed-Point Triangle Rasterizer with 2D/3D Rendering Path/
│ │ └── DFT Scan Insertion on a NoC Router: Working Around OpenLane 2's Missing DFT Support
│ ├── EDA Tools and ML-Based Design Analysis/
│ │ ├── ISCAS'85/89 Python Analysis Tool
│ │ ├── PD Congestion ML Tool
│ │ ├── Branch Pred. and Cache Replacement Eval ML Tool
│ │ ├── CSR SpMV Benchmark and Memory Roofline Analysis
│ │ └── Basic PCB Fault Detection
│ ├── Autonomous Drone for GNSS-Denied Environments (ISRO IRoC-U 2025)/
│ │ └── Simulation in Webots
│ ├── PPO-Based Reinforcement Learning for Autonomous Racing on AWS DeepRacer
│ └── Autonomous Multi-Sensor Robot Simulation (GPS/IMU/LiDAR/2-DOF Vision)/
│ ├── LFR - Basic Line Following Robot Simulation
│ ├── Obstacle Avoidance Robot
│ ├── Wall Follower Robot
│ └── Differential Drive Robot
├── blogs/
│ ├── DFT Scan Insertion on a NoC Router: Working Around OpenLane 2's Missing DFT Support
│ ├── Building a Hardware Scan-Line Triangle Rasterizer: From Single-Pixel Core to SIMD Warp Architecture
│ ├── My First Tiny Tapeout: Building a Digital PLL on Sky130
│ ├── Optimising a Pipelined RISC-V Core: From Naive Pipeline to Near-Superscalar Performance
│ ├── Hardware Approaches to Floating-Point Transcendental Function Computation: CORDIC, PR-CORDIC, and LUT+Polynomial
│ ├── Formal Verification with SymbiYosys and Yices2: Proving Your RTL Correct
│ ├── Packaging RTL IP with FuseSoC: From ALU to Published Core
│ ├── Setting Up PYNQ on Legacy Zybo (xc7z010clg400-1): Complete Boot and WiFi Guide
│ ├── High-Level Synthesis with C: A Practical Guide from Code to RTL
│ ├── PD-aware Machine Learning: Congestion, DRC, IR-Drop and Net Delay Prediction
│ ├── Analog-to-Digital Converters: Architecture Taxonomy, Analog Front-End Realities, and System-Level Selection
│ ├── Vision Language Action Models in Robotics
│ ├── Designing a 4R2W Register File: Why It's Harder Than It Looks
│ ├── Designing a Simple RTL Block for ASIC vs FPGA: A Pipelined 8-bit MAC
│ ├── Inside an Op-Amp: CMOS Implementation, Internal Structure, and Non-Idealities
│ ├── Floating Point vs Fixed Point: A Hardware-Centric Perspective
│ ├── Why RISC-V Is Better for Custom Silicon
│ ├── Introduction to VLSI Design Flow: RTL to GDSII
│ ├── Computer Vision vs. Sensor Fusion: Who Wins the Self-Driving Car Race?
│ ├── ROS 2 vs ROS 1: What Changed and Why It Matters
│ ├── What is SLAM? And Why It's the Brain of Mobile Robots
│ ├── Kociemba's Algorithm: The Two-Phase Breakthrough #PID1.5
│ ├── How Computers Solve the Rubik's Cube #PID1.4
│ ├── The Mathematics Behind the Rubik's Cube #PID1.3
│ ├── Solving the Rubik's Cube #PID1.2
│ ├── Mechanics of the Rubik's Cube #PID1.1
│ ├── All Puzzles Are the Same Problem #PID1.0
│ ├── My RosConIN'24 (+GNOME Asia Summit) Experience
│ └── 
├── guestbook/
└── contact/
what is this place
a portfolio site to document my projects in one place. most repos are private because they’re half-finished and constantly changing, so this felt like a cleaner way to track things.
blogs are here too. shifting away from theoretical posts toward documenting my actual process, failures included, rather than just finished work.
how it’s built
static site on hugo, modified from an existing theme. added latex support, image handling, seo tweaks and a bunch of other things as i needed them.
contact form runs through formspree. the guestbook works via a cloudflare worker that creates issues on a github repo, and the page reads and renders those. completely anonymous.
i’m not a sw guy, so a lot of the layout work, ui edits, and content refinement happened with help from GPT-4o, GPT-5.x, and Claude Sonnet 4.6. used them for building new layouts, editing existing ones, and cleaning up writing for blogs and such. credit where it’s due.