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Projects

INT8 Fixed-Point CNN Hardware Accelerator and Image-Processing Suite

INT8 Fixed-Point CNN Hardware Accelerator and Image-Processing Suite

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  • Designed and evaluated multiple CIFAR-10 CNNs, selecting a Pareto-optimal 6-layer residual model balancing accuracy (~84%), parameter memory (~52 kB), and compute (~12–13 M FLOPs) for hardware deployment
  • Implemented a tiling-based convolution/GEMM accelerator with reusable MAC PEs and line-buffered dataflow; integrated AXI4-Lite control + AXI-Stream/DMA data movement; verified end-to-end via RTL testbenches against Python reference models
  • Developed pipelined processing elements using 8-bit Booth–Kogge MACs, with FSM-based control and a 2-cycle ready/valid handshake, ensuring timing-clean and scalable datapath operation
  • Performed quantization studies (PTQ/QAT) from FP32 (Q1.31) to fixed-point (Q1.7), achieving ~4× memory reduction with <1% accuracy loss; validated TensorFlow FP32 to RTL numerical consistency
  • Built automation flows (TCL/Python) for ROM/weight generation, testbench stimulus, and inference execution; generated coefficient memories and ensured deterministic layer-by-layer verification
  • Implemented a streaming image-processing toolkit (AXI-Stream) including edge detection, filtering, denoising, and enhancement, with pipelined RTL and FIFO-based backpressure handling; included MLP-based (E)MNIST classifier with automated preprocessing/inference
Verilog SystemVerilog TensorFlow Python TCL Perl AXI-Stream
Design & Formal Verification of Parameterizable Fixed-Point CORDIC IP

Design & Formal Verification of Parameterizable Fixed-Point CORDIC IP

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  • Implemented shift-add datapath with all 6 modes rotation/vectoring (circular/linear/hyperbolic); width/iter/angle frac/output width–shift scaling swept across configs
  • Built trig/mag/atan2/mul/div/exp wrappers; observed ∼e-5 RMS (@32b, 16iter) baseline vs double-precision references
  • Proved handshake, deadlock-free bounded liveness, range safety, symmetry & monotonicity via SystemVerilog assertions (SymbiYosys/Yices2)
  • Auto-generated atan tables & param files via Python; FuseSoC-packaged core with documented sensitivity, error trends & failure regions
  • Variants: pipelined/SIMD/multi-issue; Systems: radix-2 FFT/IFFT, DPLL, Sigma-Delta ADC Front-End, QAM16 receiver (Costas carrier + Gardner timing recovery)
Verilog SystemVerilog SymbiYosys Yices2 Python FuseSoC
Pipelined Systolic Array for GEMM/Conv2D with MAC PPA Study (Sky130 OpenLane)

Pipelined Systolic Array for GEMM/Conv2D with MAC PPA Study (Sky130 OpenLane)

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  • Designed parameterized output-stationary 2D systolic array for signed 8-bit GEMM/Conv2D with wavefront scheduling and pipelined PEs
  • Implemented im2col-based Conv2D mapping onto GEMM core (4×16×36), achieving 42.47 MAC/cycle (99.5% peak) at 66.3% PE utilization
  • Explored 9 MAC architectures (Array/Baugh/Booth × RCA/Kogge/CSA) via full RTL-to-GDSII (OpenLane, sky130_fd_sc_hd); achieved 100 MHz timing closure with post-route STA correlation and 0 DRC/LVS violations
  • Quantified PPA tradeoffs - Booth+RCA 15.8k µm² / 537 cells (min area); Array+Kogge 5.68 ns (~176 MHz, max Fmax); Kogge ~4–5% faster at ~20% higher power; CSA ~67% larger and ~2× power with no timing gain
  • Designed ping-pong SRAM tiled GEMM with DMA-backed data movement (1-cycle buffer swap), enabling overlap of load and compute
  • Implemented direct-mapped tile cache (tag+valid) achieving 93.75% hit rate; verified across 240+ tests (GEMM/Conv, random/boundary/burst/multi-tile), confirming functional correctness and linear systolic scaling (K+M+N−2)
Verilog Sky130 RTL2GDS OpenLane DFT
Dual-Issue Superscalar RV32I CPU: Design, Verification, and Performance Evaluation

Dual-Issue Superscalar RV32I CPU: Design, Verification, and Performance Evaluation

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  • Built a two-wide in-order superscalar RISC processor with parallel IF–ID–EX–MEM–WB lanes and independent pipeline registers per lane
  • Designed dual 32-bit instruction fetch per cycle with inter-lane dependency checks, hazard suppression, and load-use stall handling
  • Implemented 4R2W register file, RAW/WAW detection, branch squashing, & multi-port memory for concurrent fetch and data access
  • Evaluated SC/MC/5-stage pipelined designs via directed programs (assembly with RISCV GCC Toolchain & QEMU reference), analyzing CPI (1/3.8/1.6), cycle counts, and hazard overhead
  • Validated RV32I compliance using the RISC-V Architectural Compliance Test (RISCV-ACT), verified functionality with the Dhrystone benchmark
  • Evaluated LUT utilization, CPI, and instruction throughput, achieving ~1.6 CPI and ~0.63 instructions/cycle throughput in the two-wide superscalar pipeline
Verilog RISC-V GCC Toolchain QEMU
Low-Power 5-Port Wormhole NoC Router

Low-Power 5-Port Wormhole NoC Router

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  • Designed 5-port wormhole router with dual-VC OpenRAM SRAM FIFOs, XY routing, crossbar, and round-robin arbiters; full PnR in OpenLane2 on sky130A
  • Cut power 70.34% via RTL clock gating on idle FIFO banks, output isolation cells, ABC AREA 2 synthesis, and coordinated CTS/resizer tuning
  • Restructured SRAM floorplan to 3-column layout; die area down 16.47%, wirelength down 5.77%, setup slack improved 13.4% after 4-stage datapath pipelining
  • Fixed two pipeline bugs (FIFO coherence race, double-grant) and removed 85 redundant registers; swapped one-hot crossbar select to eliminate 78 fanout violations
  • Built custom OpenLane2 scan steps: 720 FF-to-SDFF swap, 4-chain stitch with met2 ports, 8 bugs debugged, LVS clean
  • Gate-level ATPG on 4 submodules via Fault 0.6.1; 95.46-98.09% stuck-at coverage, remaining faults structurally undetectable
Verilog OpenLane2 OpenRAM OpenROAD Fault sky130A DFT
Pipelined Low Power ALU with Scan Chain Integration

Pipelined Low Power ALU with Scan Chain Integration

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  • Designed non-pipelined/pipelined/scan-enabled 4-stage ALU; pipeline FFs replaced with scan FFs for scan-in/capture/scan-out; added CDC bridge (async FIFO + 2FF sync) between clk domains
  • Gate-level timing analysis in Yosys/OpenSTA (Sky130) with clock uncertainty, I/O delays, & input slew; ∼1.7x fmax gain with pipelining
  • RTL2GDS flow: scan vs no-scan, single vs dual scan, CTS skew tightening, util/density & floorplan stress; closed timing throughout
  • Integrated scan-safe clock gating on pipeline regs; reduced switching power ~19% & internal power ~38% with negligible timing impact
  • Analyzed IO-driven routing effects; worst-case pinning increased clock wire length by >2x despite CTS/placement optimization; recovered via pin-arch optimization (>50% clk WL ↓); PDN stress at signoff showed +21% total & +58% switching power
Verilog Yosys OpenSTA Sky130 DFT
AHB–APB Bridge with Self-Checking Verification

AHB–APB Bridge with Self-Checking Verification

  • Designed a parameterizable AHB-Lite to APB bridge with FSM-based control supporting single & burst read/write transactions
  • Implemented address/data latching, write buffering, read return, and burst sequencing, handling pipelined and non-pipelined accesses
  • Built a self-checking SV testbench with macro-controlled test modes (single/burst R/W) and assertion-based data validation
  • Verified protocol correctness across all transaction types; additionally designed & verified standalone (I2C/SPI/UART) peripheral controllers
Verilog SystemVerilog
Functional & UVM Verification of SHA-256 Core (secworks)

Functional & UVM Verification of SHA-256 Core (secworks)

  • Developed a self-checking functional verification environment for the secworks SHA-256 core, validating compression rounds, IV initialization, message scheduling, and multi-block chaining
  • Implemented directed, random, corner-case, and fail-case stimuli (e.g., `abc`, empty message, all-zero, all-ones) to verify digest correctness and interface handshake behavior (`ready`, `digest_valid`)
  • Injected malformed control sequences, undefined inputs, and invalid block ordering to stress protocol robustness and confirm mismatch detection and failure reporting
  • Automated compilation, simulation, and log aggregation through a TCL-driven regression flow, enabling repeatable runs and consolidated verification reporting
  • Implemented a basic SystemVerilog/UVM verification environment with agent, driver, sequencer, monitor, and scoreboard to modularize stimulus generation and digest checking
Verilog Icarus Verilog TCL
FIR DSP Accelerator SoC (Sky130, Caravel)

FIR DSP Accelerator SoC (Sky130, Caravel)

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  • Designed a fixed-point DSP SoC (Sky130, Caravel) with CIC decimator → 8-tap FIR → PWM DAC pipeline
  • Implemented Wishbone-mapped control interface enabling runtime FIR coefficient updates and datapath configuration
  • Verified functionality via RTL simulations (filter response, gain, PWM linearity) using Icarus Verilog
  • Achieved timing closure at 40 MHz and clean physical signoff (OpenLane, LVS/DRC clean)
Verilog OpenLane Sky130 PDK Wishbone Icarus Verilog
Fixed-Point Triangle Rasterizer with 2D/3D Rendering Path

Fixed-Point Triangle Rasterizer with 2D/3D Rendering Path

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  • Designed a command-driven RTL graphics pipeline with triangle setup, edge-equation generation, bounding-box clamp, framebuffer clear, and configurable fog control using packed 32-bit opcodes
  • Implemented scanline rasterization using signed fixed-point arithmetic with incremental edge stepping, barycentric coverage tests, Gouraud color interpolation, and valid/ready FIFO-based module handshaking
  • Built software tooling in Python to generate scenes and animations with 3D transforms, perspective projection, backface culling, triangle depth ordering, and frame-by-frame submission into the RTL renderer
  • Validated correctness using animated scenes including rotating cubes, Rubik’s cubes, image-to-triangle reconstruction, and large multi-triangle workloads to stress throughput and ordering behavior
  • Developed an in-progress 4-lane SIMT variant using per-lane FIFOs, round-robin arbitration, shared framebuffer writes, and native RTL migration of 3D transform/depth stages
SystemVerilog Icarus Verilog Python Fixed-Point Arithmetic