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Projects

INT8 Fixed-Point CNN Hardware Accelerator and Image-Processing Suite

INT8 Fixed-Point CNN Hardware Accelerator and Image-Processing Suite

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  • Designed and evaluated multiple CIFAR-10 CNNs, selecting a Pareto-optimal 6-layer residual model balancing accuracy (~84%), 52 kB parameter memory and 12-13 M FLOPs for hardware deployment
  • Implemented a tiling-based convolution/GEMM accelerator with reusable MAC PEs and line-buffered dataflow; AXI4-Lite control with AXI-Stream/DMA data movement, verified by RTL testbenches against Python reference models
  • Developed pipelined processing elements on 8-bit Booth-Kogge MACs with FSM-based control and a 2-cycle ready/valid handshake for timing-clean, scalable datapath operation
  • Performed quantization studies (PTQ/QAT) from FP32 to Q1.7 fixed-point, achieving ~4x memory reduction with under 1% accuracy loss; validated TensorFlow FP32 to RTL numerical consistency
  • Built TCL/Python automation for ROM and weight generation, testbench stimulus and inference execution; generated coefficient memories with deterministic layer-by-layer verification
  • Implemented a streaming image-processing toolkit (AXI-Stream) with edge detection, filtering, denoising and enhancement, pipelined RTL and FIFO-based backpressure; included an MLP-based (E)MNIST classifier with automated preprocessing and inference
Verilog SystemVerilog TensorFlow Python TCL Perl AXI-Stream
Design & Formal Verification of Parameterizable Fixed-Point CORDIC IP

Design & Formal Verification of Parameterizable Fixed-Point CORDIC IP

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  • Implemented shift-add datapath with all 6 modes of rotation/vectoring over circular, linear and hyperbolic systems; width, iteration, angle fraction and output width-shift scaling swept across configs
  • Built trig/mag/atan2/mul/div/exp wrappers, observing ~4e-5 RMS at 32b and 16 iterations against double-precision references
  • Proved handshake, deadlock-free bounded liveness, range safety, symmetry and monotonicity via SystemVerilog assertions (SymbiYosys/Yices2)
  • Auto-generated atan tables and param files via Python; FuseSoC-packaged core with documented sensitivity, error trends and failure regions
  • Variants: temporal (micro-pipelined) and spatial (throughput) lanes; Systems: radix-2 FFT/IFFT, DPLL, Sigma-Delta ADC front end, QAM16 receiver with Costas carrier and Gardner timing recovery
Verilog SystemVerilog SymbiYosys Yices2 Python FuseSoC
Pipelined Systolic Array for GEMM/Conv2D with MAC PPA Study (Sky130 OpenLane)

Pipelined Systolic Array for GEMM/Conv2D with MAC PPA Study (Sky130 OpenLane)

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  • Designed parameterized output-stationary 2D systolic array for signed 8-bit GEMM/Conv2D with wavefront scheduling and pipelined PEs
  • Implemented im2col-based Conv2D mapping onto the GEMM core (4x16x36), achieving 99.5% of peak MAC/cycle at 66.3% PE utilization
  • Explored 9 MAC architectures (Array/Baugh/Booth x RCA/Kogge/CSA) through full RTL-to-GDSII on sky130_fd_sc_hd, with post-route STA correlation and 0 DRC/LVS violations
  • Quantified PPA tradeoffs: Booth+RCA smallest by area, Array+Kogge highest Fmax, Kogge 4-5% faster at ~20% higher power, CSA larger at ~2x power with no timing gain
  • Designed ping-pong SRAM tiled GEMM with DMA-backed data movement and 1-cycle buffer swap to overlap load and compute; added a tile cache on Sky130 SRAM macros (3x 1k x 8 per operand, tag+valid) at 93.75% cold hit rate
  • Compared direct-mapped, 2-way and fully-associative tile caching, keeping 2-way for its conflict behaviour at ~26% logic overhead; verified across 240+ GEMM/Conv tests (random, boundary, burst, multi-tile) and linear K+M+N-2 systolic scaling
Verilog Sky130 RTL2GDS OpenLane DFT
RISC-V RV32I(M) Processor Family: Superscalar and Out-of-Order Cores

RISC-V RV32I(M) Processor Family: Superscalar and Out-of-Order Cores

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  • Built a two-wide in-order superscalar RISC processor with parallel IF-ID-EX-MEM-WB lanes and independent pipeline registers per lane
  • Designed dual 32-bit instruction fetch per cycle with inter-lane dependency checks, hazard suppression and load-use stall handling; 4R2W register file, RAW/WAW detection, branch squashing and multi-port memory
  • Evaluated SC/MC/5-stage pipelined designs via directed programs (RISC-V GCC toolchain, QEMU reference), analysing CPI, cycle counts and hazard overhead across each pipeline depth
  • Validated RV32I compliance with the RISC-V Architectural Compliance Test (41/41) and directed regressions, checked the M extension against QEMU and Spike, and confirmed functionality with Dhrystone and 9/9 CoreMark runs
  • Extended to scalar and dual-issue Tomasulo out-of-order execution with rename, ROB commit, per-class issue queues and CDB wakeup, reaching 5.06 CoreMark/MHz alongside a branch prediction study (static, 1-bit, 2-bit, global, tournament, BTB, RAS)
  • Ran DOOM first on a Verilator prototype of the board and then on a Cyclone IV DE0-Nano with SDRAM, UART framebuffer and keyboard; ported FreeRTOS with trap unit, CLINT timer and CLI, and built a CP/M 2.2 console with RunCPM, Chip-8 and native games
Verilog Verilator Icarus Verilog Surfer Ripes RISC-V GCC/LLVM CoreMark QEMU Spike RISCOF Quartus FPGA
Low-Power 5-Port Wormhole NoC Router

Low-Power 5-Port Wormhole NoC Router

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  • Designed 5-port wormhole router with dual-VC OpenRAM SRAM FIFOs, XY routing, crossbar and round-robin arbiters; full PnR in OpenLane2 on sky130A
  • Cut power ~70% via RTL clock gating on idle FIFO banks, output isolation cells, ABC AREA 2 synthesis and coordinated CTS/resizer tuning
  • Restructured the SRAM floorplan to a 3-column layout, bringing die area down ~16% and wirelength down ~6%, with setup slack improved after 4-stage datapath pipelining
  • Fixed two pipeline bugs (FIFO coherence race, double-grant) and removed redundant registers; swapped the one-hot crossbar select to eliminate fanout violations
  • Built custom OpenLane2 scan steps: FF-to-SDFF swap, 4-chain stitch with met2 ports, bug debug through to LVS-clean signoff
  • Ran gate-level ATPG on 4 submodules with Fault, reaching ~95-98% stuck-at coverage, with the remaining faults structurally undetectable
Verilog OpenLane2 OpenRAM OpenROAD Fault sky130A DFT
Pipelined Low Power ALU with Scan Chain Integration

Pipelined Low Power ALU with Scan Chain Integration

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  • Designed non-pipelined, pipelined and scan-enabled 4-stage ALU variants; pipeline FFs replaced with scan FFs for scan-in/capture/scan-out, with an async-FIFO and 2FF sync CDC bridge between clock domains
  • Ran gate-level timing analysis in Yosys/OpenSTA on Sky130 with clock uncertainty, IO delays and input slew, showing ~1.7x fmax gain with pipelining
  • Built the RTL2GDS flow across scan vs no-scan, single vs dual scan, CTS skew tightening, util/density and floorplan stress, closing timing throughout
  • Integrated scan-safe clock gating on the pipeline registers, cutting internal power ~38% and switching power ~19% with negligible timing impact
  • Analysed IO-driven routing effects: worst-case pinning doubled clock wirelength despite CTS and placement work, with over half recovered through pin-arch changes and PDN stress characterised at signoff
Verilog Yosys OpenSTA Sky130 DFT
AHB–APB Bridge with Self-Checking Verification

AHB–APB Bridge with Self-Checking Verification

  • Designed a parameterizable AHB-Lite to APB bridge with FSM-based control supporting single and burst read/write transactions
  • Implemented address/data latching, write buffering, read return and burst sequencing, handling both pipelined and non-pipelined accesses
  • Built a self-checking SV testbench with macro-controlled test modes (single/burst R/W) and assertion-based data validation
  • Verified protocol correctness across all transaction types; additionally designed and verified standalone I2C/SPI/UART peripheral controllers
Verilog SystemVerilog
Functional & UVM Verification of SHA-256 Core (secworks)

Functional & UVM Verification of SHA-256 Core (secworks)

  • Developed a self-checking functional verification environment for the secworks SHA-256 core, validating compression rounds, IV initialization, message scheduling and multi-block chaining
  • Implemented directed, random, corner-case and fail-case stimuli ('abc', empty message, all-zero, all-ones) to verify digest correctness and interface handshake behaviour (ready, digest_valid)
  • Injected malformed control sequences, undefined inputs and invalid block ordering to stress protocol robustness and confirm mismatch detection and failure reporting
  • Automated compilation, simulation and log aggregation through a TCL-driven regression flow for repeatable runs and consolidated reporting
  • Implemented a SystemVerilog/UVM environment with agent, driver, sequencer, monitor and scoreboard to modularise stimulus generation and digest checking
Verilog Icarus Verilog TCL
FIR DSP Accelerator SoC (Sky130, Caravel)

FIR DSP Accelerator SoC (Sky130, Caravel)

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  • Designed a fixed-point DSP SoC (Sky130, Caravel) with a CIC decimator to 8-tap FIR to PWM DAC pipeline
  • Implemented a Wishbone-mapped control interface for runtime FIR coefficient updates and datapath configuration
  • Verified filter response, gain and PWM linearity through RTL simulations in Icarus Verilog
  • Achieved timing closure at 40 MHz and clean physical signoff through OpenLane, LVS/DRC clean
Verilog OpenLane Sky130 PDK Wishbone Icarus Verilog
Fixed-Point Triangle Rasterizer with 2D/3D Rendering Path

Fixed-Point Triangle Rasterizer with 2D/3D Rendering Path

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  • Designed a command-driven RTL graphics pipeline with triangle setup, edge-equation generation, bounding-box clamp, framebuffer clear and configurable fog control using packed 32-bit opcodes
  • Implemented scanline rasterization in signed fixed-point arithmetic with incremental edge stepping, barycentric coverage tests, Gouraud colour interpolation and valid/ready FIFO-based handshaking
  • Built Python tooling to generate scenes and animations with 3D transforms, perspective projection, backface culling, triangle depth ordering and frame-by-frame submission into the RTL renderer
  • Validated correctness on rotating cubes, Rubik's cubes, image-to-triangle reconstruction and large multi-triangle workloads stressing throughput and ordering behaviour
  • Added an 8-lane SIMD warp path with per-lane FIFOs, round-robin arbitration, parallel interpolation and shading, and native RTL migration of the 3D transform and depth stages, lifting throughput from 0.50 to 3.86 px/cycle
SystemVerilog Icarus Verilog Python Fixed-Point Arithmetic