AHB–APB Bridge with Self-Checking Verification

Overview

RTL Design

• Parameterizable AHB-Lite to APB bridge
• Implements single-transfer non-sequential (NONSEQ) and sequential burst (SEQ) read and write transactions
• FSM-based control path translating pipelined AHB-Lite address/data phases into two-phase APB (PSEL / PENABLE) transfers
• Address and write-data latching with burst address continuation
• Read-data return path aligned with HREADY handshaking across back-to-back and idle-separated accesses

Verification Environment

• Self-checking SystemVerilog testbench (iverilog + GTKWave)
• Macro-selected compile-time test modes:
  • SINGLE_READ
  • SINGLE_WRITE
  • BURST_READ
  • BURST_WRITE
• SystemVerilog assertions checking PSEL, PENABLE, HREADY, and address/data stability across wait states
• Automated readback comparison with PASS/FAIL summary and per-test VCD waveform dumps

Protocol Checks

• Tested single and burst read/write sequences across pipelined and non-pipelined AHB-Lite transfers
• Checked word-aligned address progression, burst continuation, and APB setup/access phase timing

Additional Work

Standalone peripheral RTL blocks verified with directed SystemVerilog testbenches:

• I2C Master Controller: Implements a single-master, multi-slave I²C bus supporting standard-mode timings, programmable SCL low/high periods, ACK/NACK handling, and clock stretching detection. Includes START/STOP generation, byte-wise transfers, and address+data framing logic.

• SPI Master (Modes 0–3): Supports CPOL/CPHA mode selection, 8-bit full-duplex transfers, configurable SCLK division, selectable slave-select behavior, and MSB-first shifting using a compact FSM and separate TX/RX shift registers.

• UART TX Soft-Core IP: Serial transmitter with a baud-rate generator, start/stop framing, data-valid gating, and single-byte shift serialization in synthesizable SystemVerilog.