CMOS Inverter Layout & Post-Layout Simulation

A complete CMOS inverter implementation built using Magic VLSI (SCMOS) for physical layout and ngspice for extracted-device simulation.
Covers device construction rules under the SCMOS process, physical layout of PMOS/NMOS devices, contact/tap structures, parasitic-aware extraction, and transient analysis of inverter switching characteristics.

The layout follows the SCMOS ruleset:

• PMOS implemented inside an n-well using p-diffusion; body tied to the well tap (VDD).
• NMOS implemented directly in the p-substrate using n-diffusion; body tied to substrate tap (GND).
• Poly crossing active regions forms the MOS channel; poly, metal1, and contact stack-up follows SCMOS vertical connectivity.
• Metal1 routes input/output rails; taps ensure reverse-biased junctions and latch-up prevention.

Extraction produces a transistor-level .spice netlist including geometry-derived parasitics.
Transient simulation evaluates:

• Static noise margins and switching point displacement due to device sizing.
• Rise/fall asymmetry from mobility difference (μₙ ≫ μₚ).
• Output slew vs. load capacitance and PMOS/NMOS drive ratio.
• Propagation delays under 1.8 V operation using level-1 MOS models.

DC Analysis Results

Transient Analysis Results