Summary

Overview

The CORDIC (COordinate Rotation DIgital Computer) algorithm performs trigonometric, hyperbolic, and linear computations using only additions and bit-shifts — no multipliers anywhere in the datapath. This implementation is a fully parameterized, synthesizable Verilog soft IP covering all six canonical modes across three coordinate systems. It has been formally verified for structural and control invariants using SymbiYosys, numerically characterized across the full parameter space, and demonstrated as the computational engine inside two production-grade RTL integrations: a Digital PLL, 16-QAM demodulator and a Radix-2 DIT FFT/IFFT.

Core Features

• Shift–add iterative datapath (no multipliers)
• 6 operating modes across 3 coordinate systems
• Deterministic latency: \( \text{ITER} + 1 \) cycles
• Clean start / busy / valid handshake
• Fully parameterized width, iterations, angle precision, scaling
• Python auto-generation of LUTs and parameter headers
• FuseSoC packaged IP
• Formal verification of control and structural invariants
• Drop-in architectural variants (iterative, pipelined, SIMD, multi-issue)
• Demonstrated integration in QAM16 demodulator, DPLL and FFT/IFFT

Operating Modes

Algorithm: Iterative Update Equations

Hyperbolic repeat schedule — certain iterations must execute twice for guaranteed convergence. Indices follow \(k_{n+1} = 3k_n + 1\):

ITER=16:  [1, 2, 3, 4, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 13, 14]

LUT Generation

The angle lookup tables must be regenerated whenever WIDTH, ITER, or ANG_FRAC change. The Python generator gen/gen_cordic_tables.py produces three auto-generated files that all downstream RTL \include`s:

cordic_atan_rom.v — LUT of \( \tan^{-1}(2^{-i}) \) for circular mode and \( \tanh^{-1}(2^{-i}) \) for hyperbolic mode, each entry in Q2.30:

atan_table[i]  = int(round(math.atan(2**-i)  * 2**FRAC_BITS))
atanh_table[i] = int(round(math.atanh(2**-i) * 2**FRAC_BITS))

cordic_params.vh — Defines WIDTH, ITER, CORDIC_K_SCALE, CORDIC_K_H_SCALE, and all bit-width macros. The gain compensation constants are:

K = 1.0
for i in range(ITER):
    K *= math.sqrt(1.0 + 2**(-2*i))
K_SCALE   = int(round((1.0 / K)   * 2**FRAC_BITS))   # circular

K_H = 1.0
for i in repeat_schedule:                              # with repeat indices
    K_H *= math.sqrt(1.0 - 2**(-2*i))
K_H_SCALE = int(round((1.0 / K_H) * 2**FRAC_BITS))   # hyperbolic

cordic_consts.vh — Defines HALF_PI, PI, TWO_PI, and SIN_COS_OUT_SHIFT in Q2.30. Never hardcode angle constants in RTL — always use this file.

Parameterization

Trade-offs explored between accuracy, latency, and area.

Accuracy — Baseline Results (WIDTH=32, ITER=16, FRAC=30)

All figures below are at the recommended production configuration. Full parameter sweep results are in the linked subproject reports.

Circular Rotation — sin / cos

OUT_WIDTH=16, OUT_SHIFT=16. Errors are symmetric and dominated by output quantization. Increasing ITER beyond 16 yields no improvement at 30-bit angle precision.

Circular Rotation — tan

Inherently ill-conditioned near ±π/2. Stable within \(|z| < 1.4\) rad; treat as best-effort outside that range.

Circular Vectoring — magnitude

MAG_OUT_WIDTH=16, MAG_OUT_SHIFT=16. Achieves lower error than rotation because no output gain correction is needed beyond K_SCALE.

Circular Vectoring — atan2

Error is dominated entirely by the \((x,y) \to (0,0)\) singularity. All non-zero inputs produce correct phase. Zero-magnitude inputs must be explicitly guarded in system logic.

Linear Rotation — mult

Q2.30 × Q2.30 → Q2.30, well-conditioned across ±0.9 input range. Production-ready.

Linear Vectoring — div

Saturates at ±2.0 due to Q2.30 representable range. Stable within range; requires prescaling for quotients outside ±2.0.

Hyperbolic Rotation — sinh / cosh

OUT_WIDTH=16, OUT_SHIFT=16. Stable and monotonic across ±1.0 input range with correct repeat schedule.

Hyperbolic Rotation — tanh

Structurally limited — error does not improve with ITER or FRAC. Treat as best-effort.

Hyperbolic Rotation — exp

OUT_SHIFT=17. Stable across ±1.0 after correct repeat scheduling.

Hyperbolic Vectoring — ln

OUT_SHIFT=16. Valid input range 0.2–1.9. Repeat schedule mandatory — without it the series fails to converge.

Known Numerical Sensitivities

Wrapper Semantics

Wrappers provide gain compensation, deterministic scaling, format conversion, and mode-specific preconditioning. Correct scaling is mandatory — underscaling causes amplitude collapse; overscaling causes sign inversion and catastrophic distortion. RMS error saturates near ~0.7–1.2 in all failure regions (deterministic, not random).

Formal Verification

Scope: Core iteration engine and control FSM
Tools: SymbiYosys + Yices2
Assertions: SystemVerilog Assertions (parametric)

Proven Structural Properties

• Single-cycle start
• Non-overlapping transactions
• Bounded progress \( \le ITER + 1 \)
• Deadlock-free execution
• Input stability while busy
• Output range safety

Rotation Mode Properties

• Odd/even symmetry
  \( \sin(-x) = -\sin(x) \)
  \( \cos(-x) = \cos(x) \)
• Local monotonicity near zero
• Sign consistency

Vectoring Mode Properties

• Magnitude symmetry across quadrants
• Correct zero-vector handling
• \( \text{atan2} \) odd symmetry
• \( \pi \)-rotation consistency

Note: Numerical precision is validated through simulation, not formal proof.

Parameterization Sweep Summary

Full parameter sensitivity reports (iteration sweeps, width sweeps, fraction-bit sweeps, output-scaling failure regions) are in the linked subproject docs for each of the six modes. Key cross-mode findings:

• ITER=16 is sufficient for all modes at 30-bit precision; beyond 16 yields no measurable improvement
• WIDTH≥32 required for stable convergence; WIDTH=40 with mismatched scaling causes catastrophic failure across all modes
• FRAC≥28 required for sin/cos/magnitude below 1×10⁻⁴ RMS
• Output scaling mismatches (wrong OUT_SHIFT) produce deterministic catastrophic failure — RMS error saturates near ~0.7–1.2 — not graceful degradation

Drop-In CORDIC Core Families

Family A — Iterative / Control-Oriented

Family B — Throughput / Feed-Forward

Family C — SIMD / Spatial

Family D — Multi-Issue / Time-Interleaved

Implementations

The CORDIC core has been integrated into two complete RTL subsystems, each independently verified with dedicated Python verification suites. Both treat cordic_core as a black-box computational primitive — no CORDIC internals leak into the integration logic.

FFT / IFFT — Radix-2 DIT, N=8

A fully synchronous N=8 FFT implemented using cordic_core in rotation mode to compute twiddle factors entirely in hardware, requiring no ROM. The IFFT is a zero-logic wrapper using the identity:

IFFT(X) = conj( FFT( conj(X) ) ) / N

Conjugation is two wire negations — din_im negated on input, dout_im negated on output. No extra logic.

N/2 parallel CORDIC instances compute twiddle factors \( W_N^k = e^{-j2\pi k/N} \) on start. Angles outside \((-\pi/2, \pi/2)\) are folded at elaboration time via localparam. The butterfly datapath uses Q1.30 with >>1 guard shift per stage to prevent overflow. Full architecture, directed tests, and sweep results are in the linked docs.

Verified metrics (WIDTH=32, ITER=16, 200 Monte-Carlo trials):

QAM16 Demodulator

A fully synchronous 16-QAM demodulator using two cordic_core instances — one in rotation mode driving the NCO for carrier synthesis, one in vectoring mode computing the exact atan2 phase error inside the Costas loop. No floating-point anywhere in the datapath. All angular quantities are Q2.30; sample-level IQ data is Q1.30 throughout. Full architecture description and verification results are in the linked docs.

Verified metrics:

Directed test results:

DPLL — Digital Phase-Locked Loop

A fully synchronous second-order Digital Phase-Locked Loop using one cordic_core instance in rotation mode driving the NCO for carrier synthesis. The phase detector uses a direct cross-product (Im{ conj(nco) × ref }) rather than CORDIC vectoring — this avoids the ±180° false-lock ambiguity that CORDIC preconditioning introduces in free-running loops. All angular quantities are Q2.30; the phase accumulator is 64-bit to safely hold TWO_PI without overflow. Full architecture description, bug log, and verification results are in the linked docs.

Verified metrics (WIDTH=32, ITER=16, KP=0.014, KI=0.0001):

Directed test results:

Sigma-Delta ADC — Bandpass with CORDIC Downconversion

A fully synchronous bandpass oversampling ADC pipeline using cordic_core in rotation mode (via cordic_nco) and cordic_mixer for digital downconversion of the decimated IF output to baseband IQ. The modulator and decimator are standalone fixed-point blocks; the CORDIC chain is identical to the carrier recovery path in qam16_demod. No floating-point anywhere. All angular quantities are Q2.30; sample data is Q1.30 throughout.

The pipeline has three stages. The 2nd-order error-feedback modulator converts the IF input to a 1-bit PDM bitstream at the oversampled rate using two 64-bit integrators — the same sign-extended accumulator pattern as dpll_loop_filter. A 3rd-order CIC decimator (56-bit accumulators, supports OSR up to 256) filters and downsamples by OSR, producing a Q1.30 IF PCM sample. The cordic_nco and cordic_mixer then shift the IF PCM to baseband IQ — freq_adj can be driven directly from a DPLL or Costas loop output for closed-loop carrier recovery, making this the natural front-end for the QAM16 demodulator in an SDR chain.

IF input (Q1.30, OSR×fs)
    │
    ▼
[sd_adc]          2nd-order SD modulator, LFSR dither, ±2³¹ anti-windup
    │  1-bit PDM at OSR×fs
    ▼
[sd_decimator]    3rd-order CIC, decimate by OSR, normalize >>>3×log₂(OSR)
    │  IF PCM (Q1.30 at fs)
    ▼
[cordic_nco]  ◄── phase_inc (carrier at PCM rate, Q2.30)
[cordic_mixer]    complex multiply: pcm × conj(nco)
    │  bb_i / bb_q (Q1.30 baseband IQ at fs)
    ▼
  Output  ──►  qam16_demod  /  dpll  (freq_adj feedback)

Full architecture description, bug log, and verification results are in the linked docs.

Verified metrics (WIDTH=32, ITER=16, OSR=64, DITHER_EN=1):

Directed test results (tb_sd_adc.v, 8 tests):

Bandpass test results (tb_sd_bandpass.v, 3 tests):

Toolchain