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CNN Models for CIFAR-10

Model Architectures

MODEL_ARCH_1

[ (Conv2D → BN)×2 → MaxPool → Dropout(0.3) ]
→ [ (Conv2D → BN)×2 → MaxPool → Dropout(0.4) ]
→ [ (Conv2D → BN)×2 → MaxPool → Dropout(0.5) ]
→ Flatten → Dense(512) → BN → Dropout(0.5) → Dense(10, softmax)

  • Number of Parameters: 3,251,018
  • Test Accuracy: 90.91%
MODEL_ARCH_1
MODEL_ARCH_2

[ (Conv2D(32) → BN)×2 → MaxPool → Dropout(0.25) ]
→ [ (Conv2D(64) → BN)×2 → MaxPool → Dropout(0.35) ]
→ [ (Conv2D(128) → BN)×2 → MaxPool → Dropout(0.4) ]
→ Flatten → Dense(256) → BN → Dropout(0.5) → Dense(10, softmax)

  • Number of Parameters: 815,530
  • Test Accuracy: 88.84%
MODEL_ARCH_2
MODEL_ARCH_3

[ Conv2D(32)×2 → MaxPool ]
→ [ Conv2D(64)×2 → MaxPool ]
→ [ Conv2D(96) → MaxPool ]
→ Flatten → Dense(256) → Dense(10, softmax)

  • Number of Parameters: 517,002
  • Test Accuracy: 85.53%
MODEL_ARCH_3
MODEL_ARCH_4

[ Conv2D(16)×2 → MaxPool ]
→ [ Conv2D(32)×2 → MaxPool ]
→ [ Conv2D(64)×2 → MaxPool ]
→ GAP → Dense(10, softmax)

  • Number of Parameters: 72,730
  • Test Accuracy: 83.05%
MODEL_ARCH_4

Model Architecture Summary

Model IDNumber of ParametersTest Accuracy (%)Model Size (MB)
MODEL_ARCH_13,251,01890.9112.40
MODEL_ARCH_2815,53088.843.11
MODEL_ARCH_3517,00285.531.97
MODEL_ARCH_472,73083.050.28

Model size calculated assuming 32-bit floating-point weights (params × 4 bytes ÷ 1024²).

Verilog Inference Q-Point Results

All results are based on a test set of 100 images (10 from each class). The local test accuracy is therefore considered equal to the number of correct predictions out of 100.

All evaluations use the final model [MODEL_ARCH_4] listed in the table above.

FormatPython Accuracy (%)Verilog Accuracy (%)Notes
Float32 (Python) vs Float64 IEEE-754 (Verilog real)8584Verilog used double precision; the minor accuracy difference is not due to precision loss
Q1.318484High-precision fixed-point; results match exactly
Q1.15848416-bit fixed-point; results match exactly
Q1.782~82Moderate precision; Verilog value estimated from Python result
Q1.365~65Low precision; Verilog value estimated from Python result