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ImProVe and its Sub-projects

IMage PROcessing using VErilog
IMage PROcessing using VErilog

ImProVe (IMage PROcessing using VErilog) is a project focused on implementing image processing techniques using Verilog. It involves building image processing logic from the ground up, exploring various algorithms and approaches within HDL

Level: Beginner

Status: Ongoing

Type: Individual

Tags: FPGA, Verilog, HDL, Digital, Image Processing

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NEural NEtwork in VERilog
NEural NEtwork in VERilog

Never (NEural NEtwork in VERilog) implements a neural network in Verilog for better hardware acceleration of image processing tasks

Level: Beginner

Status: Ongoing

Type: Individual

Tags: Verilog, HDL, Digital, Image Processing, ML

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Verilog HDL Toolkit for Image Processing and Pattern Recognition

Duration: Individual, Ongoing
Tools: Verilog (Icarus Verilog, Xilinx Vivado) | Python (OpenCV, NumPy, Tkinter) | Scripting (TCL. Perl)

  • Designed image processing algorithms (e.g., edge detection, geometric & color transforms, noise reduction) in Verilog, utilizing hardware optimized math techniques to maximize computational efficiency; fine-tuned for low-latency preprocessing in embedded vision SoCs
  • Implemented 3-layer MLP (784-256-128-62) for Extended-MNIST Character Recognition (62 classes, ∼124k samples) using FSM-controlled neural network in Verilog; achieved >90% training accuracy with <5s inference latency (in simulation); developed full end-to-end preprocessing and inference workflow
  • Automated model inference and performance metric evaluation via Tcl/Perl scripts (py & iverilog commands execution); real-time Tkinter GUI for test user input
  • Working on real life applications including label detection, document scanning, stereo depth map generation, and neural network inference for MNIST/EMNIST datasets




  • I highly recommend checking out the main project, as this is just a subset. The main project focuses on image processing algorithms, and working on ImProVe (IMage PROcessing using VErilog) has made the learning curve for this project much easier.

  • NeVer (Neural Network in Verilog) is one of my favorite subprojects under ImProVe. In this subproject, my goal is to implement a fully functional neural network purely in Verilog and optimize it for efficient hardware acceleration.

Please note that the names of these projects are not meant to be taken too seriously. The names like ImProVe or NeVer may not fully reflect their functions – ImProVe doesn’t actually improve images, but processes them, and NeVer isn’t about something “never-implemented” – many have done it before. The names just make it easier for me to organize folders and code




Tabular Summary of all technical details ( NN Inference Workflow )
ParameterValue / DetailTechnical Highlights
Accuracy>90%High classification precision on both MNIST (10 classes) and EMNIST (62 classes).
Inference Latency<5 sec per predictionAchieved via a tightly controlled FSM-driven sequential evaluation in simulation.
PipeliningCoarse-grainedFinite State Machine (FSM) orchestrates layer-by-layer processing without fine-grained, parallel overlap.
Data TypeIEEE 754 realSimulation relies on IEEE 754 floating-point (non-synthesizable) for high-precision computation during development.
Python LibrariesNumPy exclusivelyUtilizes NumPy for all training routines and parameter extraction, without relying on higher-level ML frameworks.
DatasetEMNIST ByClass ≈124k (≈2K per class, 62 classes); MNIST – TSD (Google Colab)Separate datasets: EMNIST ByClass, with 62 classes (digits and both uppercase and lowercase letters), and MNIST (handwritten digits 0-9), trained independently for alphanumeric character recognition tasks.
Training OptimizersAdam (1500 iterations) + SGD with Momentum (500 iterations)Hybrid optimization: Adam for rapid convergence initially, then SGD with Momentum for fine-tuning and refinement.
Neural Architecture (MNIST)784 (input) – 128 (hidden) – 10 (output)A compact feed-forward architecture optimized for digit recognition.
Neural Architecture (EMNIST)784 (input) – 256 (hidden) – 128 (hidden) – 62 (output)Expanded design to support 62 classes (digits, uppercase, lowercase) within the same inference infrastructure.
Weight & Bias Scaling×10,000Parameters are scaled to simulate fixed-point arithmetic, ensuring compatibility during inference in Verilog.
Input Image Format28×28 grayscaleImages are captured via a Tkinter drawing interface, then processed to 28×28 grayscale before vectorization.
Preprocessing PipelineCustom Python scripts for initial image conversion + Verilog modulesWorkflow includes image conversion (img2bin.py), image processing (resize, contrast, gray, roi, padding, invert, rotate, flip, flatten), and file preparation for memory module generation.
Memory Module GenerationPython scripts (wtbs_loader.py, memloader_from_inp_vec.py)Automated conversion of weight, bias, and image vector files into synthesizable Verilog memory modules.
Simulation EnvironmentIcarus VerilogCompilation and simulation are conducted using Icarus Verilog with dedicated testbenches for module validation.
Automation & WorkflowFully automated, cross-platformIntegration via Makefiles (Linux/macOS), batch scripts (Windows), plus Perl and TCL scripts to streamline build, test, and simulation phases.
Verification & TestbenchesImplementedRobust testbenches facilitate both unit-level and end-to-end verification of the Verilog inference modules.
System IntegrationEnd-to-End pipelineSeamless integration connects Python for image input/output with Verilog for core logic simulation, creating a unified hardware prototyping workflow
Test User InteractionTkinter-based interfaceDirect interactive drawing capability allows real-time testing of handwritten inputs through the complete conversion and inference flow.