NoC Router Physical Design on sky130A
Design Under Work
5-port wormhole Network-on-Chip router written in Verilog, targeting the SkyWater 130nm open-source process node (sky130A) with the sky130_fd_sc_hd high-density standard cell library. The full physical design flow runs on OpenLane 2, Classic flow.
Ports: Local, North, South, East, West.
Each input port has two virtual channels. Each VC is backed by a synchronous FIFO implemented on a single-port SRAM macro (sram_1rw_16x16) generated by OpenRAM. 5 input ports x 2 VCs = 10 input FIFOs. Each of the 5 output ports has its own SRAM-backed FIFO. Total SRAM instances: 15 macros.
Routing is XY. The destination field in the HEAD flit determines the output port. Contention is resolved by a crossbar, a switch allocator, and a set of round-robin arbiters. Flit width is 16 bits.
Clock period was 25 ns for the low-power experiments and tightened to 20 ns for the pipelining work.
Results Summary
Part 1: Low Power
| Run | Power | vs Base | Die Area (um²) | Wirelength (um) | Hold | Setup | Slew | Notes |
|---|---|---|---|---|---|---|---|---|
| base | 2,577,878.5 | 0% | 1,824,020 | 140,132 | 42 | 0 | 789 | baseline |
| baseopt | 1,129,917.0 | -56.17% | 1,829,730 | 144,640 | 18 | 0 | 830 | RTL clock gating |
| basecgiso | 1,095,670.4 | -57.50% | 1,830,030 | 142,056 | 112 | 0 | 801 | + isolation cells |
| basecgisoopt | 1,052,925.4 | -59.16% | 1,830,820 | 147,129 | 0 | 0 | 879 | + synth opts, first timing-clean run |
| area1 | 981,842.9 | -61.91% | 1,830,380 | 143,817 | 6 | 0 | 820 | AREA 1 strategy |
| area2 | 764,607.6 | -70.34% | 1,829,840 | 138,621 | 136 | 0 | 878 | AREA 2 strategy, best power |
| area3 | FAILED | — | — | — | — | — | — | ORFS script, unresolvable hold |
| noresizer | FAILED | — | — | — | — | — | — | no resizer, hold unfixable |
| area2cts | 764,607.6 | -70.34% | 1,829,840 | 152,592 | 0 | 0 | 45 | area2 + CTS/resizer tuning |
| area2fp | 764,607.6 | -70.34% | 1,528,380 | 143,786 | 1 | 0 | 47 | floorplan shrunk to 1800x1800 um |
Total power reduction baseline to final: 70.34%. Die area reduction: 16.47%.
Part 2: Pipelining
| Metric | Non-pipelined | Pipelined |
|---|---|---|
| Sequential cells | 500 | 615 |
| Standard cell area (um²) | 60,051 | 65,464 |
| Setup WS at SS corner (ns) | 8.73 | 9.90 |
| Hold violations at SS corner | 14 | 0 |
| Hold WNS worst (ns) | -0.951 | -0.256 |
| Hold buffers inserted | 468 | 696 |
| Fanout violations | 78 | 72 |
| Switching power (W) | 0.003135 | 0.004005 |
4-stage pipeline. Two functional bugs found and fixed. Three structural optimizations applied after functional correctness was confirmed.
Part 3: DFT
| Metric | Value |
|---|---|
| Total flip-flops replaced | 720 |
| Scan chains created | 4 |
| Scan ports | scan_in_1..4, scan_out_1..3, scan_enable_1 |
| Scan port layer | met2, left die edge |
| Sequential cell area before (um²) | 18,918 |
| Sequential cell area after (um²) | 23,516 |
| Area increase | 24.3% |
| Flow stages completed | 75 / 75 |
| LVS | Pass |
| DRC errors | 132 (all nwell.4, all inside SRAM macros) |
Two custom OpenROADStep subclasses written to implement scan insertion inside OpenLane 2. 8 bugs encountered and resolved.
Part 4: ATPG
| Module | Cut Netlist Lines | Fault Coverage | Runtime |
|---|---|---|---|
| rr_arbiter | 433 | 96.43% | 5.00s |
| switch_allocator | 2,722 | 95.46% | 7.12s |
| vc_fifo | not recorded | 98.09% | 10.60s |
| input_unit | 11,688 | 96.59% | 17.22s |
All four modules exceeded 95% stuck-at fault coverage. Remaining uncovered faults are structurally undetectable in each case.
Known Issue: SRAM DRC Violations
All 132 DRC errors reported across every run in this project are nwell.4 violations located inside the SRAM macro instance boundaries. Zero routing DRC errors exist on the standard cell or interconnect layers.
OpenRAM-generated macros for sky130 use an optimized SRAM-specific layout. The abstract LEF used during PnR exposes only the external metal interface. When Magic runs DRC on the assembled design, it sees the nwell regions from the macro boundary without the internal tap cell geometry that satisfies the nwell.4 rule. The official OpenLane documentation and the SkyWater PDK known issues page both document this. These errors are not caused by any work in this project. They appear identically on every run including the unmodified baseline.
Metrics Collection
All runs produce final/metrics.json from the OpenLane 2 signoff steps.
- Power: OpenSTA static analysis at tt_025C_1v80.
- Timing: Worst-case across 9 corners: tt_025C_1v80, ss_100C_1v60, ff_n40C_1v95, each crossed with min/nom/max parasitic extraction corners.
- IR drop: OpenROAD PSM on power and ground nets.
- Routing DRC: OpenROAD DRT.
- Physical DRC and LVS: Magic and KLayout.