preloader

Basic RV32I RTL CPU Design

TL-Verilog Based RV32I Core
TL-Verilog Based RV32I Core

This version focuses on designing a RISC-V core using TL-Verilog, a high-level hardware description language, via the Makerchip platfor

Status: Ongoing

Type: Individual

Tags: RISC-V, TL-Verilog

View Project

No projects found for the selected tags.

Basic RV32I RTL CPU Design

NEVER
NameROSE
DescriptionRoSe (RISC-V Open-Source Environment) is a set of learning-focused experiments exploring the design of a RISC-V processor using only open-source tools. Each version tackles a different aspect of CPU design—from simulation to high-level abstraction to physical design. These are standalone efforts and not part of a continuous development flow.
StartMar 2025
RepositoryROSE🔗
TypeIndividual
LevelBeginner
SkillsComputer Architechture
Tools UsedTL-Verilog, Colab, Xilinx, OpenLane
Current StatusOngoing






RoSe: RISC-V Open-Source Env

RoSe (RISC-V Open-Source Environment) is a set of learning-focused experiments exploring the design of a RISC-V processor using only open-source tools. Each version tackles a different aspect of CPU design—from simulation to high-level abstraction to physical design. These are standalone efforts and not part of a continuous development flow.

Colab-Based Verilog Simulation

An entry-level setup for simulating a RISC-V CPU using Verilog and Icarus Verilog, hosted on Google Colab. This environment allows testing of instruction execution using C or Assembly code compiled for the RISC-V architecture.

Tools Used
  • Icarus Verilog: Open-source Verilog compiler and simulator.
  • RISC-V GCC Toolchain: Compiles high-level C or assembly into RISC-V binaries.
How It Works
  • Write and compile RISC-V C/Assembly code using the GCC toolchain.
  • Convert binaries to a memory format usable by Verilog testbenches.
  • Simulate instruction execution using a Verilog-based CPU model in Icarus Verilog.
Current Status
  • ALU implemented and tested.
  • Able to run simple arithmetic and logic instructions.
  • Environment runs entirely in the browser via Colab, making it accessible and easy to replicate.

TL-Verilog Based RV32I Core

This version focuses on designing a RISC-V core using TL-Verilog, a high-level hardware description language, via the Makerchip platform.

Tools Used
  • TL-Verilog: A language offering higher abstraction over traditional RTL Verilog.
  • Makerchip: A web-based IDE for TL-Verilog development and simulation, including waveform visualization and real-time debugging.
Highlights
  • Pipelined architecture with modular stages (IF, ID, EX, MEM, WB).
  • Real-time simulation and debugging features for rapid development.
  • Clean separation of control and datapath logic due to TL-Verilog’s structure.
Current Status
  • Working RV32I CPU core implemented.
  • Successfully runs compiled RISC-V assembly programs.
  • Simulated and tested through Makerchip’s integrated environment.

OpenLANE Physical Design Setup

This version explores backend design concepts—synthesizing RTL to GDSII—using the OpenLANE toolchain on a local Linux Mint setup.

Tools Used
  • OpenLANE: Open-source digital ASIC flow (RTL-to-GDSII).
  • Yosys: RTL synthesis tool.
  • OpenROAD, Magic, KLayout: Used for placement, routing, verification, and layout inspection.
Objective
  • Take small designs (like PicoRV32 or a custom ALU) through a full physical design flow.
  • Learn the steps involved in chip implementation: synthesis, floorplanning, placement, clock tree synthesis, routing, and DRC.
Current Status
  • Environment fully set up on Linux Mint.
  • Currently working on characterization and synthesis of the PicoRV32 core.
  • RTL blocks are being prepared for integration into the OpenLANE flow.