Verilog HDL Toolkit for Image Processing and Pattern RecognitionDesigned custom image preprocessing algorithms (edge detection, noise reduction, transforms) directly in Verilog for hardware-efficient, low-latency operation. Implemented a 64-bit FSM-driven 3-layer MLP (784-256-128-62) for EMNIST classification (>90% accuracy, >75% simulation acc, ~1.5s simulated inference), with automated simulation pipelines, GUI-based input testing, and cross-language integration using Python, Tcl, and Perl.
