Designing a 4R2W Register File: Why It’s Harder Than It Looks
A hands-on deep dive into building a 4-read, 2-write register file in Verilog — architectural tradeoffs, structural hazards, and practical RTL fixes.
ASIC Design
Designing a Simple RTL Block for ASIC vs FPGA: A Pipelined 8-bit MAC
A practical comparison of designing the same hardware block for ASIC and FPGA — architecture, RTL style, constraints, and physical implications.