An FPGA is a grid of logic and programmable wires. You load a bitstream and the chip becomes whatever circuit you described. Basic elements Every FPGA, Xilinx …
FPGA
Xilinx
Altera
tag · 2 posts
LUT
OPENSOURCE (4)
SUPERSCALAR (4)
ASIC DESIGN (3)
BENCHMARKING (3)
COREMARK (3)
DSP (3)
ECOSYSTEM (3)
FIXED POINT (3)
FPGA (3)
FPGA DESIGN (3)
OPTIMISATION (3)
PERFORMANCE ANALYSIS (3)
RISC-V (3)
SKY130 (3)
SYMBIYOSYS (3)
VERILATOR (3)
ALGORITHMS (2)
ASIC (2)
AUTONOMOUS SYSTEMS (2)
COMPUTER VISION (2)
CORDIC (2)
DOOM (2)
ENOB (2)
FLOATING POINT (2)
FORMAL VERIFICATION (2)
FUTURE TRENDS (2)
GDS (2)
IEEE 754 (2)
KALMAN FILTER (2)
LIDAR (2)
LOCALIZATION (2)
LUT (2)
OOO (2)
PHYSICAL DESIGN (2)
ROBOTICS (2)
RTL (2)
SENSOR FUSION (2)
SYNTHESIS (2)
SYSTEMVERILOG (2)
TIMING CLOSURE (2)
VERILOG (2)
3D MAPPING (1)
3D PRINTING (1)
4R2W (1)
A* SEARCH (1)
ACADEMIC RESEARCH (1)
ACTION (1)
ACTIONS (1)
ADAS (1)
ADC (1)
AI (1)
AI INTEGRATION (1)
ALGORITHM ANALYSIS (1)
ALGORITHM EFFICIENCY (1)
ALGORITHMIC THINKING (1)
ALM (1)
ALTERA (1)
ALU (1)
ANALOG CIRCUITS (1)
ARM CORTEX-A9 (1)
ARRAY PARTITION (1)
ASIC PROTOTYPING (1)
ASSEMBLY (1)
ATPG (1)
AUTONOMOUS DRIVING (1)
AXI-STREAM (1)
AXI4 (1)
BACKTRACKING (1)
BARYCENTRIC INTERPOLATION (1)
BEGINNER'S METHOD (1)
BFS (1)
BOUNDED MODEL CHECKING (1)
BRAIN TEASERS (1)
BRAM (1)
BYPASS LOGIC (1)
C TO RTL (1)
CAMERA (1)
CAN IT RUN DOOM (1)
CFOP (1)
CIRCUITNET (1)
CLB (1)
CLI (1)
CLOCK JITTER (1)
CMOS ANALOG DESIGN (1)
COCOTB (1)
COGNITIVE SKILLS (1)
COMBINATORICS (1)
COMMUNITY SUPPORT (1)
COMPILERS (1)
COMPUTATIONAL COMPLEXITY (1)
COMPUTER ARCHITECTURE (1)
CONFERENCE RECAP (1)
CONGESTION PREDICTION (1)
CORE FILE (1)
CROSS SOLVING (1)
CSR (1)
CUBE INTERNALS (1)
CUBE NOTATION (1)
CUBE SOLVER (1)
CURRENT MIRROR (1)
CUSTOM EXTENSIONS (1)
CYCLE NOTATION (1)
CYCLONE IV (1)
DDS (1)
DE0-NANO (1)
DEADLOCK (1)
DEBUGGING (1)
DEEP LEARNING (1)
DFS (1)
DFT (1)
DHCP (1)
DIFFERENTIAL PAIR (1)
DPLL (1)
DRC (1)
DRC PREDICTION (1)
DSP BLOCKS (1)
EDA ML (1)
EDA TOOLS (1)
EDALIZE (1)
EDGE EQUATIONS (1)
EDUCATIONAL GAMES (1)
EFFICIENCY (1)
EMBEDDED LINUX (1)
EMBEDDED SOCS (1)
ENGINEERING INSIGHTS (1)
ENUMERATION (1)
ESP32-C3 (1)
ETHERNET SETUP (1)
FAULT (1)
FFT (1)
FINE-TUNING (1)
FIRST TWO LAYERS (1)
FIXED-POINT ARITHMETIC (1)
FLASH ADC (1)
FLOORPLANNING (1)
FOCUS TRAINING (1)
FPGA PROTOTYPING (1)
FPGA SOC (1)
FREERTOS (1)
FREQUENCY COMPENSATION (1)
FRICTION (1)
FRONT-END DESIGN (1)
FUSESOC (1)
GAIN STAGE (1)
GDSII (1)
GDSTK (1)
GNN (1)
GNOME ASIA SUMMIT (1)
GOURAUD SHADING (1)
GROUP THEORY (1)
HANDSHAKE (1)
HARDWARE ACCELERATION (1)
HARDWARE ARITHMETIC (1)
HARDWARE BRING-UP (1)
HARDWARE EXPLORATION (1)
HARDWARE GRAPHICS (1)
HAZARDS (1)
HEURISTICS (1)
HLS (1)
HOBBY IDEAS (1)
ICARUS VERILOG (1)
IMPLEMENTATION (1)
INTRODUCTION (1)
IP PACKAGING (1)
IR DROP (1)
ISA (1)
IVERILOG (1)
KERNEL MODULES (1)
KEYNOTES (1)
KLAYOUT (1)
KOCIEMBA ALGORITHM (1)
LAB (1)
LANGUAGE (1)
LAUNCH FILES (1)
LAYER-BY-LAYER (1)
LOOKUP TABLES (1)
LOOP UNROLLING (1)
LVS (1)
MAC UNIT (1)
MACHINE LEARNING (1)
MAINTENANCE (1)
MAPPING (1)
MARCO PLACER (1)
MATERIALS (1)
MATH FOUNDATIONS (1)
MECHANICAL DESIGN (1)
MENTAL EXERCISE (1)
MICROARCHITECTURE (1)
MIDDLEWARE (1)
MIGRATION PATH (1)
MIXED-SIGNAL DESIGN (1)
MOBILE ROBOTS (1)
MODDING (1)
MODELS (1)
MODULARITY (1)
MOTIVATION (1)
MULTIPORT MEMORY (1)
NET DELAY PREDICTION (1)
NETLIST EXTRACTION (1)
NETWORKING (1)
NOC (1)
NODE LIFECYCLE (1)
NOISE SHAPING (1)
NON UNIFORM QUANTIZATION (1)
NONLINEARITY (1)
NOTATION (1)
OFFSET VOLTAGE (1)
OLL (1)
OPAMP (1)
OPEN SOURCE (1)
OPEN SOURCE HARDWARE (1)
OPEN-SOURCE CORES (1)
OPEN-SOURCE RTL (1)
OPENLANE (1)
OPENLANE 2 (1)
OPENROAD (1)
OPENVLA (1)
OPTIMAL SOLUTIONS (1)
PARTICLE FILTER (1)
PATH PLANNING (1)
PERCEPTION (1)
PERFORMANCE BENCHMARKS (1)
PERFORMANCE TUNING (1)
PERMUTATIONS (1)
PERSONAL (1)
PHASE 1 (1)
PHASE 2 (1)
PIECE TYPES (1)
PIPELINE (1)
PIPELINE ADC (1)
PLACE AND ROUTE (1)
PLACEMENT ALGO (1)
PLL (1)
POLYNOMIAL (1)
POWER ANALYSIS (1)
PRACTICE DRILLS (1)
PROBABILISTIC ROBOTICS (1)
PROBLEM-SOLVING (1)
PROOFS (1)
PRUNING TABLES (1)
PUZZLE AUTOMATION (1)
PUZZLE BENEFITS (1)
PYNQ (1)
PYUVM (1)
Q FORMAT (1)
QEMU (1)
QOS SETTINGS (1)
QUANTIZATION (1)
RADAR (1)
RASTERIZATION (1)
REAL-TIME SYSTEMS (1)
REFERENCE DESIGN (1)
REGISTER FILE (1)
RESET VERIFICATION (1)
RETRO GAME (1)
RETRO GAMES (1)
RL (1)
ROBOT NAVIGATION (1)
ROBOTICS ALGORITHMS (1)
ROBOTICS COMMUNITY (1)
ROBOTICS PERCEPTION (1)
ROBOTICS SOFTWARE (1)
ROS 1 (1)
ROS 2 (1)
ROSCONIN (1)
ROTATION AXES (1)
ROUNDING ERROR (1)
RTL DESIGN (1)
RTL VERIFICATION (1)
RTL WORKFLOW (1)
RTL8188GU (1)
RTOS (1)
RUBIK'S CUBE INTRO (1)
RUBIK'S MATH (1)
RUNTIME ANALYSIS (1)
SAMPLING THEORY (1)
SAR ADC (1)
SBY (1)
SCAN CONVERSION (1)
SCAN INSERTION (1)
SDRAM (1)
SEARCH ALGORITHMS (1)
SEARCH SPACE REDUCTION (1)
SECURITY (1)
SECURITY FEATURES (1)
SENSORS (1)
SHAPELY (1)
SHOULDICE FLOW (1)
SIFIVE (1)
SIGMA-DELTA ADC (1)
SILICON (1)
SIMULATION (1)
SIMULTANEOUS LOCALIZATION AND MAPPING (1)
SKILL DEVELOPMENT (1)
SKILL SCRIPTS (1)
SKYWATER (1)
SLAM (1)
SLEW RATE (1)
SLIDESHARE (1)
SNDR (1)
SNR (1)
SOFTWARE DESIGN (1)
SOLVER COMPARISON (1)
SPATIAL REASONING (1)
SPEAKER INTERVIEWS (1)
SPEEDCUBING BASICS (1)
SPIKE (1)
STANDARD CELLS (1)
STAR BATTLE (1)
STARFIVE (1)
STATE GRAPH (1)
STATE SPACE (1)
STOICHIOMETRY (1)
SVA (1)
SYMMETRY (1)
SYNTHESISABLE RTL (1)
SYSTEMVERILOG ASSERTIONS (1)
TAKEAWAYS (1)
TALK HIGHLIGHTS (1)
TAPEOUT (1)
THEORETICAL CS (1)
TINY TAPEOUT (1)
TOLERANCES (1)
TOMASULO (1)
TOOLCHAIN (1)
TOPICS & SERVICES (1)
TRAINING (1)
TRANSCENDENTAL (1)
TRAPS (1)
TWO-PHASE SOLVER (1)
U-NET (1)
UART (1)
VERIFICATION (1)
VISION (1)
VITIS HLS (1)
VIVADO HLS (1)
VLA (1)
WIFI DRIVER (1)
WORKSHOPS (1)
XC7Z010 (1)
XILINX (1)
YICES2 (1)
ZYBO (1)
ZYNQ (1)
ZYNQ-7000 (1)
Hardware Approaches to Floating-Point Transcendental Function Computation: CORDIC, PR-CORDIC, and LUT+Polynomial
hardware
computer-architecture
rtl
fpga
Computing sin(x), cos(x), arctan(x), e^x, and ln(x) in hardware is not as obvious as it sounds. Software on a general-purpose CPU offloads these to a …
CORDIC
transcendental
IEEE-754