Featured Projects
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INT8 Fixed-Point CNN Hardware Accelerator and Image-Processing Suite
- Designed a synthesizable shallow Res-CNN for CIFAR-10, Pareto-optimal among 8 CNNs for throughput, latency, and accuracy
- Built systolic-array PEs with 8-bit CSA–MBE MACs, FSM-based control, 2-cycle read/valid handshake, and verified TB operation
- Performed PTQ/QAT (Q1.31→Q1.3) analysis; Q1.7 PTQ retained ~84% accuracy (<1% loss) with 4× smaller (~52 kB) memory footprint
- Auto-generated 14 coefficient & 3 RGB ROMs via TCL/Python automation; validated TF/FP32–RTL consistency and automated inference execution
- Implemented digital image-processing toolkit (edge, denoise, filter, enhance) and MLP classifier on (E)MNIST (>75% accuracy) with GUI visualization
AHB–APB Bridge with Self-Checking Verification
- Designed a parameterizable AHB-Lite to APB bridge with FSM-based control supporting single and burst read/write transactions
- Implemented address and data latching, write buffering, read response handling, and burst sequencing for pipelined and non-pipelined accesses
- Developed a self-checking SystemVerilog testbench with macro-controlled test modes (single/burst read/write) and assertion-based data validation
- Verified protocol correctness across all transaction types; additionally designed and verified standalone I2C, SPI, and UART peripheral controllers
Pipelined ALU with Scan-Chain Integration
- Designed non-pipelined, pipelined, and scan-enabled 4-stage ALU variants; replaced pipeline flip-flops with scan flip-flops to support scan-in, capture, and scan-out operations
- Performed gate-level timing analysis using Yosys and OpenSTA (Sky130) with clock uncertainty, I/O delays, and input slew, achieving ~1.7× fmax improvement through pipelining
- Executed full RTL-to-GDS flow comparing scan vs. no-scan and single vs. dual-scan configurations; tightened CTS skew, explored utilization/density trade-offs, and closed timing across all cases
- Analyzed I/O-driven routing effects, observing worst-case pin placements increasing clock wire length by over 2× despite CTS and placement optimization
- Recovered clock routing efficiency via pin-architecture optimization, reducing clock wire length by over 50%; signoff PDN stress analysis showed +21% total power and +58% switching power
RISC-V & MIPS Microarchitectures - SC / MC / Pipelined / Dual-Issue Superscalar
- Designed a two-wide in-order superscalar 16-bit RISC processor with parallel IF–ID–EX–MEM–WB pipelines and independent per-lane pipeline registers
- Implemented dual-instruction fetch per cycle with inter-lane dependency checking, hazard suppression logic, and load–use stall handling
- Built a 4R2W multi-ported register file with RAW/WAW hazard detection, branch squashing, and concurrent instruction/data memory access
- Evaluated single-cycle, multi-cycle, and 5-stage pipelined designs using directed test programs, analyzing CPI (1 / 3.8 / 1.6), cycle counts, and hazard-induced overhead
EDA TOOLS
- Python Tool for Analysis & Fault-Modeling (ISCAS’85/’89 Benchmark)
- Predictive ML-EDA Framework for Early Routability & Timing Sign-off (CircuitNet14)
- PCB Fault Classification and Detection (Akhatova/PCB-Defects | YOLOv7)
CMOS Bandgap Reference Simulation
- Simulated and verified a CMOS bandgap reference in OSU 180 nm CMOS using LTspice at a nominal 3.3 V supply
- Validated first-order temperature compensation by analyzing PTAT, CTAT, and Vref behavior across −40 °C to 200 °C
- Evaluated line regulation via DC supply sweeps from 2 V to 4 V and measured Vref sensitivity using waveform cursors
- Performed 100-run Monte Carlo mismatch analysis and quantified Vref variation with a standard deviation of 4.6 mV
Two-Stage CMOS Op-Amp with Miller Compensation
- Designed an NMOS differential input pair with PMOS current-mirror load and common-source gain stage using Miller compensation, achieving 53.1 dB DC gain and 4.35 MHz unity-gain bandwidth
- Derived transistor sizing from slew-rate, input common-mode range, and gain constraints; verified correct biasing with a stable 0.60 V operating point
- Measured a 9.6 kHz −3 dB frequency, 448× small-signal gain, and clean 0.14–1.03 V output swing with no observable nonlinear distortion
- Evaluated key performance metrics including 1 mW power dissipation, 32 dB CMRR, 64.6/80.8 dB PSRR±, and 10 V/µs slew rate, confirming loop stability
CMOS Inverter Layout & Post-Layout Simulation
- Built a CMOS inverter layout in Magic VLSI (SCMOS), including PMOS in n-well, NMOS in p-substrate, taps and contacts, and M1 routing; achieved DRC-clean layout
- Performed DC analysis in Ngspice on the extracted netlist to evaluate VTC behavior, observing VOH ~1.8 V, VOL ~0 V, and switching threshold VM ~0.95 V at 27 °C
- Analyzed transient switching behavior at 1.8 V operation, measuring TPHL ~282 ps, TPLH ~216 ps, and rise/fall times of ~0.50/0.53 ns
- Evaluated dynamic performance versus load conditions; observed average power ~2.51 µW and average current ~1.40 µA using Level-1 MOS models
Analog Function Generator with Adjustable Amplitude, Offset, Phase, Modulation & VCO
- Designed an op-amp–based function generator using TL082, generating sine, square (<200 ns rise/fall), and triangular waveforms
- Implemented amplitude (±10 V), DC offset (±5 V), and phase control (0°–160°) over a 1 kHz–500 kHz operating range using a first-order all-pass filter
- Built the signal chain using a Wien-bridge oscillator, Schmitt trigger, integrator, and CD4051 multiplexer; validated via LTspice simulation and TI ASLK Pro hardware
- Integrated AM and PM modulation blocks along with a relaxation-oscillator-based VCO in LTspice, using unity-gain buffers to minimize inter-stage loading
Semiconductor Device Modeling using Sentaurus TCAD
- Modeled N-resistor, PN diode, and NMOS devices in Sentaurus TCAD with parameterized doping profiles and device geometries
- Configured and automated process and device simulations using Sentaurus Workbench with command-based scripting workflows
- Analyzed and visualized electrostatic potential, carrier concentration distributions, and I–V characteristics using Sentaurus Visual and Inspect tools
Autonomous Drone for GNSS-Denied Environments (ISRO IRoC-U 2025)
- Integrated NVIDIA Jetson Nano for onboard compute with Pixhawk 4 flight controller to enable autonomous navigation and precision landing
- Designed a sub-2 kg quadrotor optimized for GNSS-denied mapping, localization, and vision-based safe-zone detection
- Calibrated ESCs and implemented a stable 5 V / 3 A BEC power system; established bidirectional long-range telemetry using ESP32 (~500 m)
- Interfaced barometer, optical-flow, and stereo-vision sensors with Pixhawk over I2C and UART for fused state estimation
- Implemented visual–inertial odometry using ORB-SLAM3 and VINS-Fusion on ROS 2, achieving ~5 m localization with <5 cm drift
- Simulated Mars-like no-GPS flight scenarios in Webots with 0.38 g gravity, enabling autonomous landings within 1.5 m × 1.5 m safe zones
PPO-Based Reinforcement Learning for Autonomous Racing on AWS DeepRacer
- Trained continuous-action PPO agents on AWS SageMaker for end-to-end, camera-based autonomous racing with steering and speed control
- Designed reward functions emphasizing centerline stability, heading alignment, curvature-aware waypoint tracking, and velocity-weighted progress
- Stabilized training using distance-band shaping, steering smoothness constraints, and tuned PPO hyperparameters (entropy annealing, ε-clipping, GAE λ)
- Evaluated robustness under simulated perturbations including waypoint jitter, curvature sweeps, and speed-limit randomization
- Achieved consistent sub-2-minute lap times, outperforming default baselines and reaching top global leaderboard rankings in 2024
Autonomous Multi-Sensor Robot Simulation (GPS/IMU/LiDAR/2-DOF Vision)
- Developed a fully simulated 4-wheel autonomous robot equipped with GPS, 9-axis IMU, 2D LiDAR, ultrasonic distance sensors, and an actively actuated 2-DOF camera system
- Implemented global position tracking, local free-space detection, camera-based object observation, and reactive obstacle avoidance within the simulation stack
- Modeled sensor fusion inputs including GPS (x,y), IMU orientation/angular velocity, LiDAR ranging, and short-range distance sensing for collision-free navigation
- Designed independent wheel velocity control enabling smooth translation and turning, with teleoperation and autonomous wandering modes
- Built as a baseline multi-sensor robotics testbed for evaluating classical navigation and control behaviors without SLAM or learning-based methods